41     AspeedSDHCIState *sdhci = opaque;  in aspeed_sdhci_read()  local
45         val = extract64(sdhci->slots[0].capareg, 0, 32);  in aspeed_sdhci_read()
48         val = extract64(sdhci->slots[0].capareg, 32, 32);  in aspeed_sdhci_read()
51         val = extract64(sdhci->slots[0].maxcurr, 0, 32);  in aspeed_sdhci_read()
54         val = extract64(sdhci->slots[1].capareg, 0, 32);  in aspeed_sdhci_read()
57         val = extract64(sdhci->slots[1].capareg, 32, 32);  in aspeed_sdhci_read()
60         val = extract64(sdhci->slots[1].maxcurr, 0, 32);  in aspeed_sdhci_read()
64             val = sdhci->regs[TO_REG(addr)];  in aspeed_sdhci_read()
80     AspeedSDHCIState *sdhci = opaque;  in aspeed_sdhci_write()  local
87         sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;  in aspeed_sdhci_write()
90         sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg,  in aspeed_sdhci_write()
94         sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg,  in aspeed_sdhci_write()
98         sdhci->slots[0].maxcurr = deposit64(sdhci->slots[0].maxcurr,  in aspeed_sdhci_write()
102         sdhci->slots[1].capareg = deposit64(sdhci->slots[1].capareg,  in aspeed_sdhci_write()
106         sdhci->slots[1].capareg = deposit64(sdhci->slots[1].capareg,  in aspeed_sdhci_write()
110         sdhci->slots[1].maxcurr = deposit64(sdhci->slots[0].maxcurr,  in aspeed_sdhci_write()
115             sdhci->regs[TO_REG(addr)] = (uint32_t)val;  in aspeed_sdhci_write()
134     AspeedSDHCIState *sdhci = opaque;  in aspeed_sdhci_set_irq()  local
137         sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n);  in aspeed_sdhci_set_irq()
139         qemu_irq_raise(sdhci->irq);  in aspeed_sdhci_set_irq()
141         sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n);  in aspeed_sdhci_set_irq()
143         qemu_irq_lower(sdhci->irq);  in aspeed_sdhci_set_irq()
150     AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);  in aspeed_sdhci_realize()  local
151     AspeedSDHCIClass *asc = ASPEED_SDHCI_GET_CLASS(sdhci);  in aspeed_sdhci_realize()
155                                         sdhci, NULL, sdhci->num_slots);  in aspeed_sdhci_realize()
157     sysbus_init_irq(sbd, &sdhci->irq);  in aspeed_sdhci_realize()
158     memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,  in aspeed_sdhci_realize()
159                           sdhci, TYPE_ASPEED_SDHCI, 0x1000);  in aspeed_sdhci_realize()
160     sysbus_init_mmio(sbd, &sdhci->iomem);  in aspeed_sdhci_realize()
162     for (int i = 0; i < sdhci->num_slots; ++i) {  in aspeed_sdhci_realize()
163         Object *sdhci_slot = OBJECT(&sdhci->slots[i]);  in aspeed_sdhci_realize()
164         SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);  in aspeed_sdhci_realize()
180         memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100,  in aspeed_sdhci_realize()
181                                     &sdhci->slots[i].iomem);  in aspeed_sdhci_realize()
187     AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);  in aspeed_sdhci_reset()  local
189     memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);  in aspeed_sdhci_reset()
191     sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0;  in aspeed_sdhci_reset()
192     if (sdhci->num_slots == 2) {  in aspeed_sdhci_reset()
193         sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1;  in aspeed_sdhci_reset()
195     sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;  in aspeed_sdhci_reset()
227     dc->desc = "ASPEED 2400 SDHCI Controller";  in aspeed_2400_sdhci_class_init()
236     dc->desc = "ASPEED 2500 SDHCI Controller";  in aspeed_2500_sdhci_class_init()
245     dc->desc = "ASPEED 2600 SDHCI Controller";  in aspeed_2600_sdhci_class_init()
254     dc->desc = "ASPEED 2700 SDHCI Controller";  in aspeed_2700_sdhci_class_init()