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/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
H A Drockchip-pcie-phy.txt2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
14 - #phy-cells: must be 0
16 Required properties for per-lane PHY mode (preferred):
17 - #phy-cells: must be 1
[all …]
H A Drockchip-emmc-phy.txt2 -----------------------
5 - compatible: rockchip,rk3399-emmc-phy
6 - #phy-cells: must be 0
7 - reg: PHY register address offset and length in "general
11 - clock-names: Should contain "emmcclk". Although this is listed as optional
14 See ../clock/clock-bindings.txt for details.
15 - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
16 - drive-impedance-ohm: Specifies the drive impedance in Ohm.
19 - rockchip,enable-strobe-pulldown: Enable internal pull-down for the strobe
20 line. If not set, pull-down is not used.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3399-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 Clock and Reset Unit
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3399 clock controller generates and supplies clock to various
19 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
24 clock-output-names:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Dcdn-dp-rockchip.txt1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
[all …]
H A Drockchip,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3288-mipi-dsi
19 - rockchip,rk3399-mipi-dsi
[all …]
H A Drockchip,analogix-dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - rockchip,rk3288-dp
17 - rockchip,rk3399-edp
23 clock-names:
26 - const: dp
[all …]
H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Yao <markyao0591@gmail.com>
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
24 - rockchip,rk3328-dw-hdmi
25 - rockchip,rk3399-dw-hdmi
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-rk3x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
25 - const: rockchip,rk3188-i2c
26 - const: rockchip,rk3228-i2c
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3399";
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
[all …]
H A Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Drockchip-dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/rockchip-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Wu <david.wu@rock-chips.com>
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk3399-board-spl.c1 // SPDX-License-Identifier: GPL-2.0+
83 void *blob = spl_image->fdt_addr; in spl_perform_fixups()
88 * Inject the ofpath of the device the full U-Boot (or Linux in in spl_perform_fixups()
89 * Falcon-mode) was booted from into the FDT, if a FDT has been in spl_perform_fixups()
95 boot_ofpath = spl_decode_boot_device(spl_image->boot_device); in spl_perform_fixups()
107 "u-boot,spl-boot-device", boot_ofpath); in spl_perform_fixups()
135 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; in board_debug_uart_init() local
142 /* Enable early UART0 on the RK3399 */ in board_debug_uart_init()
143 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
146 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/rk3399/
H A Dsyscon_rk3399.c1 // SPDX-License-Identifier: GPL-2.0+
12 { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF },
13 { .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
14 { .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
15 { .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
28 dev->driver_data = dev->driver->of_match->data; in rk3399_syscon_bind_of_platdata()
29 debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); in rk3399_syscon_bind_of_platdata()
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Drockchip,rk3399-dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description:
[all …]
/openbmc/u-boot/drivers/net/
H A Dgmac_rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Rockchip GMAC ethernet IP driver for U-Boot
24 #include <dt-bindings/clock/rk3288-cru.h>
58 pdata->clock_input = true; in gmac_rockchip_ofdata_to_platdata()
60 pdata->clock_input = false; in gmac_rockchip_ofdata_to_platdata()
62 /* Check the new naming-style first... */ in gmac_rockchip_ofdata_to_platdata()
63 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); in gmac_rockchip_ofdata_to_platdata()
64 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); in gmac_rockchip_ofdata_to_platdata()
67 if (pdata->tx_delay == -ENOENT) in gmac_rockchip_ofdata_to_platdata()
68 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); in gmac_rockchip_ofdata_to_platdata()
[all …]
/openbmc/u-boot/drivers/video/rockchip/
H A Drk3399_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
27 int vop_id = uc_plat->source_id; in rk3399_hdmi_enable()
28 struct rk3399_grf_regs *grf = priv->grf; in rk3399_hdmi_enable() local
31 rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK, in rk3399_hdmi_enable()
34 return dw_hdmi_enable(&priv->hdmi, edid); in rk3399_hdmi_enable()
40 struct dw_hdmi *hdmi = &priv->hdmi; in rk3399_hdmi_ofdata_to_platdata()
42 hdmi->i2c_clk_high = 0x7a; in rk3399_hdmi_ofdata_to_platdata()
43 hdmi->i2c_clk_low = 0x8d; in rk3399_hdmi_ofdata_to_platdata()
68 { .compatible = "rockchip,rk3399-dw-hdmi" },
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Drockchip-spdif.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Heiko Stuebner <heiko@sntech.de>
20 - const: rockchip,rk3066-spdif
21 - const: rockchip,rk3228-spdif
22 - const: rockchip,rk3328-spdif
23 - const: rockchip,rk3366-spdif
24 - const: rockchip,rk3368-spdif
[all …]
/openbmc/linux/drivers/soc/rockchip/
H A Dgrf.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * clock-framework and the mmc controllers making them unreliable.
138 .compatible = "rockchip,rk3036-grf",
141 .compatible = "rockchip,rk3128-grf",
144 .compatible = "rockchip,rk3228-grf",
147 .compatible = "rockchip,rk3288-grf",
150 .compatible = "rockchip,rk3328-grf",
153 .compatible = "rockchip,rk3368-grf",
156 .compatible = "rockchip,rk3399-grf",
159 .compatible = "rockchip,rk3566-pipe-grf",
[all …]
H A Dio-domain.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
28 * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
76 struct regmap *grf; member
84 struct rockchip_iodomain *iod = supply->iod; in rk3568_iodomain_write()
89 switch (supply->idx) { in rk3568_iodomain_write()
93 b = supply->idx; in rk3568_iodomain_write()
95 b = supply->idx + 4; in rk3568_iodomain_write()
98 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); in rk3568_iodomain_write()
99 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val1); in rk3568_iodomain_write()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Drockchip,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
18 Please refer to pinctrl-bindings.txt in this directory for details of the
26 various pad settings such as pull-up, etc.
29 defined as gpio sub-nodes of the pinmux controller.
34 - rockchip,px30-pinctrl
35 - rockchip,rk2928-pinctrl
36 - rockchip,rk3036-pinctrl
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
25 #include <linux/phy/phy-mipi-dphy.h>
64 "dphy-ref",
65 "dphy-cfg",
66 "grf",
98 /* below is for rk3399 only */
110 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
[all …]

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