/openbmc/linux/Documentation/devicetree/bindings/riscv/ |
H A D | cpus.yaml | 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml# 50 - const: riscv 56 - const: riscv 57 - const: riscv # Simulator only 67 https://riscv.org/specifications/ 70 - riscv,sv32 71 - riscv,sv39 72 - riscv,sv48 73 - riscv,sv57 74 - riscv,none [all …]
|
H A D | extensions.yaml | 4 $id: http://devicetree.org/schemas/riscv/extensions.yaml# 31 const: riscv 34 riscv,isa: 39 https://riscv.org/specifications/ 43 Notably, riscv,isa was defined prior to the creation of the 48 insensitive, letters in the riscv,isa string must be all 54 riscv,isa-base: 62 riscv,isa-extensions: 116 encoding") of the riscv-v-spec. 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. [all …]
|
/openbmc/linux/drivers/gpu/drm/tegra/ |
H A D | riscv.c | 11 #include "riscv.h" 32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument 34 writel(value, riscv->regs + offset); in riscv_writel() 37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument 39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors() 40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors() 41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors() 47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors() 62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors() 69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument [all …]
|
/openbmc/linux/arch/riscv/ |
H A D | Makefile | 58 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima 59 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima 60 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd 61 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c 62 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v 68 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei 72 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause 76 KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\… 78 KBUILD_AFLAGS += -march=$(riscv-march-y) 95 KBUILD_CFLAGS += $(call cc-option,-mno-riscv-attribute) [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/perf/ |
H A D | riscv,pmu.yaml | 4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml# 31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc 35 const: riscv,pmu 37 riscv,event-to-mhpmevent: 54 riscv,event-to-mhpmcounters: 68 riscv,raw-event-to-mhpmcounters: 93 "riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ] 103 compatible = "riscv,pmu"; 104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>; 105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>, [all …]
|
/openbmc/qemu/hw/riscv/ |
H A D | opentitan.c | 23 #include "hw/riscv/opentitan.h" 28 #include "hw/riscv/boot.h" 120 mc->default_ram_id = "riscv.lowrisc.ibex.ram"; in opentitan_machine_class_init() 161 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", in lowrisc_ibex_soc_realize() 167 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", in lowrisc_ibex_soc_realize() 170 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, in lowrisc_ibex_soc_realize() 255 create_unimplemented_device("riscv.lowrisc.ibex.gpio", in lowrisc_ibex_soc_realize() 257 create_unimplemented_device("riscv.lowrisc.ibex.spi_device", in lowrisc_ibex_soc_realize() 259 create_unimplemented_device("riscv.lowrisc.ibex.i2c", in lowrisc_ibex_soc_realize() 261 create_unimplemented_device("riscv.lowrisc.ibex.pattgen", in lowrisc_ibex_soc_realize() [all …]
|
H A D | sifive_e.c | 39 #include "target/riscv/cpu.h" 40 #include "hw/riscv/riscv_hart.h" 41 #include "hw/riscv/sifive_e.h" 42 #include "hw/riscv/boot.h" 152 mc->default_ram_id = "riscv.sifive.e.ram"; in sifive_e_machine_class_init() 186 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, in type_init() 188 object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon, in type_init() 204 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", in sifive_e_soc_realize() 263 create_unimplemented_device("riscv.sifive.e.qspi0", in sifive_e_soc_realize() 265 create_unimplemented_device("riscv.sifive.e.pwm0", in sifive_e_soc_realize() [all …]
|
/openbmc/qemu/configs/targets/ |
H A D | riscv32-linux-user.mak | 2 TARGET_BASE_ARCH=riscv 3 TARGET_ABI_DIR=riscv 4 TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x… 8 TARGET_SYSTBL_ABI=common,32,riscv,memfd_secret
|
H A D | riscv64-linux-user.mak | 2 TARGET_BASE_ARCH=riscv 3 TARGET_ABI_DIR=riscv 4 TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x… 8 TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret
|
H A D | riscv64-softmmu.mak | 2 TARGET_BASE_ARCH=riscv 5 …l/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-…
|
H A D | riscv64-bsd-user.mak | 2 TARGET_BASE_ARCH=riscv 3 TARGET_ABI_DIR=riscv 4 TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x…
|
H A D | riscv32-softmmu.mak | 2 TARGET_BASE_ARCH=riscv 4 TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x…
|
/openbmc/linux/arch/riscv/boot/dts/sifive/ |
H A D | fu540-c000.dtsi | 26 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 32 riscv,isa = "rv64imac"; 36 compatible = "riscv,cpu-intc"; 41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 53 mmu-type = "riscv,sv39"; 55 riscv,isa = "rv64imafdc"; 60 compatible = "riscv,cpu-intc"; 65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 77 mmu-type = "riscv,sv39"; 79 riscv,isa = "rv64imafdc"; [all …]
|
H A D | fu740-c000.dtsi | 26 compatible = "sifive,bullet0", "riscv"; 33 riscv,isa = "rv64imac"; 37 compatible = "riscv,cpu-intc"; 42 compatible = "sifive,bullet0", "riscv"; 54 mmu-type = "riscv,sv39"; 57 riscv,isa = "rv64imafdc"; 61 compatible = "riscv,cpu-intc"; 66 compatible = "sifive,bullet0", "riscv"; 78 mmu-type = "riscv,sv39"; 81 riscv,isa = "rv64imafdc"; [all …]
|
/openbmc/qemu/docs/specs/ |
H A D | riscv-iommu.rst | 9 The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU 13 riscv-iommu-pci reference device 27 $ qemu-system-riscv64 -M virt -device riscv-iommu-pci,[optional_pci_opts] (...) 52 -device riscv-iommu-pci,addr=1.0,vendor-id=0x1efd,device-id=0xedf1 \ 61 -device riscv-iommu-pci,addr=1.0,vendor-id=0x1efd,device-id=0xedf1 \ 68 use the riscv-iommu-pci device with the existing kernel support we need to emulate 74 -device riscv-iommu-pci,vendor-id=0x1efd,device-id=0xedf1 (...) 86 .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf 88 .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/
|
/openbmc/u-boot/board/emulation/qemu-riscv/ |
H A D | qemu-riscv.c | 36 ret = ofnode_read_u64(chosen_node, "riscv,kernel-start", in board_late_init() 39 ret = ofnode_read_u32(chosen_node, "riscv,kernel-start", in board_late_init() 54 * in the device tree using the riscv,kernel-start and riscv,kernel-end 73 ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-start", 0); in ft_board_setup() 75 ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-start", 0); in ft_board_setup() 81 ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-end", 0); in ft_board_setup() 83 ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-end", 0); in ft_board_setup()
|
/openbmc/openbmc/poky/meta/recipes-devtools/qemu/qemu/ |
H A D | fix-strerrorname_np.patch | 4 Subject: [PATCH] target/riscv/kvm: do not use non-portable strerrorname_np() 13 Fixes: commit 082e9e4a58ba (target/riscv/kvm: improve 'init_multiext_cfg' error 19 target/riscv/kvm/kvm-cpu.c | 3 +-- 22 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c 24 --- a/target/riscv/kvm/kvm-cpu.c 25 +++ b/target/riscv/kvm/kvm-cpu.c
|
/openbmc/linux/Documentation/devicetree/bindings/cpu/ |
H A D | idle-states.yaml | 265 Documentation/devicetree/bindings/riscv/cpus.yaml 268 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc 306 - riscv,idle-state 317 riscv,sbi-suspend-param: 718 compatible = "riscv"; 720 riscv,isa = "rv64imafdc"; 721 mmu-type = "riscv,sv48"; 727 compatible = "riscv,cpu-intc"; 734 compatible = "riscv"; 736 riscv,isa = "rv64imafdc"; [all …]
|
/openbmc/linux/arch/riscv/boot/dts/thead/ |
H A D | th1520.dtsi | 20 compatible = "thead,c910", "riscv"; 22 riscv,isa = "rv64imafdc"; 31 mmu-type = "riscv,sv39"; 34 compatible = "riscv,cpu-intc"; 41 compatible = "thead,c910", "riscv"; 43 riscv,isa = "rv64imafdc"; 52 mmu-type = "riscv,sv39"; 55 compatible = "riscv,cpu-intc"; 62 compatible = "thead,c910", "riscv"; 64 riscv,isa = "rv64imafdc"; [all …]
|
/openbmc/linux/drivers/clocksource/ |
H A D | timer-riscv.c | 11 #define pr_fmt(fmt) "riscv-timer: " fmt 25 #include <clocksource/timer-riscv.h> 149 pr_err("RISCV timer registration failed [%d]\n", error); in riscv_timer_init_common() 157 "riscv-timer", &riscv_clock_event); in riscv_timer_init_common() 169 "clockevents/riscv/timer:starting", in riscv_timer_init_common() 172 pr_err("cpu hp setup state failed for RISCV timer [%d]\n", in riscv_timer_init_common() 200 child = of_find_compatible_node(NULL, NULL, "riscv,timer"); in riscv_timer_init_dt() 203 "riscv,timer-cannot-wake-cpu"); in riscv_timer_init_dt() 210 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
|
/openbmc/linux/arch/riscv/kernel/ |
H A D | cpu.c | 53 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid() 69 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid() 82 if (!of_property_present(node, "riscv,isa-extensions")) in riscv_early_of_processor_hartid() 85 if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || in riscv_early_of_processor_hartid() 86 of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || in riscv_early_of_processor_hartid() 87 of_property_match_string(node, "riscv,isa-extensions", "a") < 0) { in riscv_early_of_processor_hartid() 96 pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"", in riscv_early_of_processor_hartid() 101 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_early_of_processor_hartid() 102 pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", in riscv_early_of_processor_hartid() 129 if (of_device_is_compatible(node, "riscv")) { in riscv_of_parent_hartid() [all …]
|
/openbmc/u-boot/arch/riscv/dts/ |
H A D | ae350_64.dts | 27 compatible = "riscv"; 28 riscv,isa = "rv64imafdc"; 29 mmu-type = "riscv,sv39"; 36 compatible = "riscv,cpu-intc"; 49 compatible = "andestech,riscv-ae350-soc"; 53 compatible = "riscv,plic0"; 58 riscv,ndev=<71>; 63 compatible = "riscv,plic1"; 68 riscv,ndev=<1>; 73 compatible = "riscv,plmt0";
|
H A D | ae350_32.dts | 27 compatible = "riscv"; 28 riscv,isa = "rv32imafdc"; 29 mmu-type = "riscv,sv32"; 36 compatible = "riscv,cpu-intc"; 49 compatible = "andestech,riscv-ae350-soc"; 53 compatible = "riscv,plic0"; 58 riscv,ndev=<71>; 63 compatible = "riscv,plic1"; 68 riscv,ndev=<1>; 73 compatible = "riscv,plmt0";
|
/openbmc/linux/arch/riscv/boot/dts/microchip/ |
H A D | mpfs.dtsi | 18 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 24 riscv,isa = "rv64imac"; 30 compatible = "riscv,cpu-intc"; 36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 48 mmu-type = "riscv,sv39"; 50 riscv,isa = "rv64imafdc"; 58 compatible = "riscv,cpu-intc"; 64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 76 mmu-type = "riscv,sv39"; 78 riscv,isa = "rv64imafdc"; [all …]
|
/openbmc/openbmc/poky/meta/recipes-multimedia/ffmpeg/ffmpeg/ |
H A D | 0001-lavc-h264dsp-move-RISC-V-fn-pointers-to-.data.rel.ro.patch | 11 libavcodec/riscv/h264dsp_rvv.S | 2 +- 14 diff --git a/libavcodec/riscv/h264dsp_rvv.S b/libavcodec/riscv/h264dsp_rvv.S 16 --- a/libavcodec/riscv/h264dsp_rvv.S 17 +++ b/libavcodec/riscv/h264dsp_rvv.S
|