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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/net/adi,adin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
[all …]
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
[all …]
H A Dxlnx,gmii-to-rgmii.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx GMII to RGMII Converter
10 - Harini Katakam <harini.katakam@amd.com>
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
24 const: xlnx,gmii-to-rgmii-1.0
29 description: The ID number for the phy.
31 phy-handle:
[all …]
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
H A Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
17 - $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
22 - ti,am654-icssg-prueth # for AM65x SoC family
32 dma-names:
34 - const: tx0-0
[all …]
H A Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
[all …]
H A Dengleder,tsnep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/engleder,tsnep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gerhard Engleder <gerhard@engleder-embedded.com>
13 - $ref: ethernet-controller.yaml#
26 interrupt-names:
29 - const: mac
30 - const: txrx-1
31 - const: txrx-2
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/ti,dp83867.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
34 nvmem-cells:
[all …]
H A Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
17 - $ref: snps,dwmac.yaml#
22 - qcom,qcs404-ethqos
23 - qcom,sa8775p-ethqos
24 - qcom,sc8280xp-ethqos
25 - qcom,sm8150-ethqos
[all …]
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
21 - compatible
26 - enum:
27 - starfive,jh7110-dwmac
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
16 - Vladimir Oltean <vladimir.oltean@nxp.com>
21 - nxp,sja1105e
22 - nxp,sja1105t
23 - nxp,sja1105p
24 - nxp,sja1105q
[all …]
H A Darrow,xrs700x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/arrow,xrs700x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - George McCollister <george.mccollister@gmail.com>
18 RGMII ports and one RMII port and are managed via i2c or mdio.
23 - enum:
24 - arrow,xrs7003e
25 - arrow,xrs7003f
[all …]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmvme7100.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
10 /include/ "mpc8641si-pre.dtsi"
37 phy-handle = <&phy0>;
38 phy-connection-type = "rgmii-id";
42 phy0: ethernet-phy@1 {
45 phy1: ethernet-phy@2 {
48 phy2: ethernet-phy@3 {
51 phy3: ethernet-phy@4 {
57 phy-handle = <&phy1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
117 phy-mode = "rgmii-id";
118 phy-handle = <&ethernet_phy0>;
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev24 This attribute contains the 32-bit PHY Identifier as reported
26 This ID is used to match the device with the appropriate
41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
44 xaui, 10gbase-kr, unknown
60 32-bit hexadecimal number representing a bit mask of the
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
37 stdout-path = "serial0:115200n8";
128 phy-mode = "rgmii-id";
129 phy-handle = <&ethernet_phy0>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dethernet.txt3 - local-mac-address: array of 6 bytes, specifies the MAC address that was
5 - mac-address: array of 6 bytes, specifies the MAC address that was last used by
7 the device by the boot program is different from the "local-mac-address"
9 - max-speed: number, specifies maximum speed in Mbit/s supported by the device;
10 - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
12 - phy-mode: string, operation mode of the PHY interface; supported values are
13 "mii", "gmii", "sgmii", "qsgmii", "tbi", "rev-mii", "rmii", "rgmii", "rgmii-id",
14 "rgmii-rxid", "rgmii-txid", "rtbi", "smii", "xgmii"; this is now a de-facto
16 - phy-connection-type: the same as "phy-mode" property but described in ePAPR;
17 - phy-handle: phandle, specifies a reference to a node representing a PHY
[all …]
H A Dfsl-tsec-phy.txt1 * TSEC-compatible ethernet nodes
5 - compatible : Should be "fsl,tsec"
6 - reg : Offset and length of the register set for the device
7 - phy-handle : See ethernet.txt file in the same directory.
8 - phy-connection-type : See ethernet.txt file in the same directory. This
9 property is only really needed if the connection is of type "rgmii-id",
10 "rgmii-rxid" and "rgmii-txid" as all other connection types are detected
17 phy-handle = <&phy0>;
18 phy-connection-type = "sgmii";
30 - compatible : Should define the compatible device type for the
[all …]
/openbmc/u-boot/include/
H A Dphy_interface.h1 /* SPDX-License-Identifier: GPL-2.0+ */
44 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
48 [PHY_INTERFACE_MODE_RGMII] = "rgmii",
49 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
50 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
51 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
58 [PHY_INTERFACE_MODE_25G_AUI] = "25g-aui",
62 [PHY_INTERFACE_MODE_NCSI] = "NC-SI",
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-aoncrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
[all …]

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