arm/dts/zynqmp-zc1751-xm018-dc4.dts

1 // SPDX-License-Identifier: GPL-2.0+
3  * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 	model = "ZynqMP zc1751-xm018-dc4";
17 	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
37 		stdout-path = "serial0:115200n8";
128 	phy-mode = "rgmii-id";
129 	phy-handle = <&ethernet_phy0>;
130 	ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
133 	ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
136 	ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
139 	ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
146 	phy-mode = "rgmii-id";
147 	phy-handle = <&ethernet_phy7>;
152 	phy-mode = "rgmii-id";
153 	phy-handle = <&ethernet_phy3>;
158 	phy-mode = "rgmii-id";
159 	phy-handle = <&ethernet_phy8>;
171 	clock-frequency = <400000>;
176 	clock-frequency = <400000>;
183 		compatible = "m25p80", "spi-flash"; /* 32MB */
184 		#address-cells = <1>;
185 		#size-cells = <1>;
187 		spi-tx-bus-width = <1>;
188 		spi-rx-bus-width = <4>; /* also DUAL configuration possible */
189 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
190 		partition@qspi-fsbl-uboot { /* for testing purpose */
191 			label = "qspi-fsbl-uboot";
194 		partition@qspi-linux { /* for testing purpose */
195 			label = "qspi-linux";
198 		partition@qspi-device-tree { /* for testing purpose */
199 			label = "qspi-device-tree";
202 		partition@qspi-rootfs { /* for testing purpose */
203 			label = "qspi-rootfs";