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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
86 * @returns 0 if ok, -1 on error (invalid clock id)
114 * Reset a peripheral. This puts it in reset, waits for a delay, then takes
115 * it out of reset and waits for th delay again.
117 * @param periph_id peripheral to reset
123 * Put a peripheral into or out of reset.
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq5018-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
26 - description: Board XO source
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H A Dqcom,ipq9574-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
18 include/dt-bindings/clock/qcom,ipq9574-gcc.h
19 include/dt-bindings/reset/qcom,ipq9574-gcc.h
23 const: qcom,ipq9574-gcc
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H A Dqcom,qcm2290-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on QCM2290
10 - Loic Poulain <loic.poulain@linaro.org>
16 See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
20 const: qcom,qcm2290-dispcc
24 - description: Board XO source
25 - description: Board active-only XO source
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H A Dqcom,sdx75-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SDX75
10 - Imran Shaik <quic_imrashai@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
17 See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
21 const: qcom,sdx75-gcc
25 - description: Board XO source
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H A Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
17 include/dt-bindings/clock/qcom,videocc-sc7180.h
18 include/dt-bindings/clock/qcom,videocc-sc7280.h
19 include/dt-bindings/clock/qcom,videocc-sdm845.h
20 include/dt-bindings/clock/qcom,videocc-sm8150.h
21 include/dt-bindings/clock/qcom,videocc-sm8250.h
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H A Dqcom,sm8450-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
17 include/dt-bindings/clock/qcom,sm8450-gpucc.h
18 include/dt-bindings/clock/qcom,sm8550-gpucc.h
19 include/dt-bindings/reset/qcom,sm8450-gpucc.h
24 - qcom,sm8450-gpucc
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H A Dqcom,sm8550-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8550
10 - Bjorn Andersson <andersson@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
20 const: qcom,sm8550-gcc
24 - description: Board XO source
25 - description: Sleep clock source
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H A Dqcom,sc7280-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Clock & Reset Controller on SC7280
10 - Taniya Das <quic_tdas@quicinc.com>
16 See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
20 const: qcom,sc7280-camcc
24 - description: Board XO source
25 - description: Board XO active source
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H A Dqcom,gcc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8350
10 - Vinod Koul <vkoul@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
20 const: qcom,gcc-sm8350
24 - description: Board XO source
25 - description: Sleep clock source
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H A Dqcom,gcc-sm8450.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8450
10 - Vinod Koul <vkoul@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
20 const: qcom,gcc-sm8450
24 - description: Board XO source
25 - description: Sleep clock source
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H A Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
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H A Dqcom,gcc-sc7280.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SC7280
10 - Taniya Das <quic_tdas@quicinc.com>
16 See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
20 const: qcom,gcc-sc7280
24 - description: Board XO source
25 - description: Board active XO source
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H A Dqcom,camcc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Clock & Reset Controller on SM8250
10 - Jonathan Marek <jonathan@marek.ca>
16 See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
20 const: qcom,sm8250-camcc
24 - description: AHB
25 - description: Board XO source
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/openbmc/linux/drivers/video/fbdev/via/
H A Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
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/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/
H A Dhost-powerreset5 # Provide source directive to shellcheck.
6 # shellcheck source=meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/powe…
7 source /usr/libexec/phosphor-state-manager/power-cmd
9 # TODO: check power status before do power reset
10 # Set state effecter state: Entity ID 0x0000 for host power control, 0x4 for power reset
12 if ! pldmtool raw -d 0x80 0x02 0x39 0x00 0x00 0x01 0x00 0x04 -m "$EID"
14 msg="Failed to set host$1 power reset"
18 echo "Host$1 is power reset"
/openbmc/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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/openbmc/linux/arch/arm/mach-omap1/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
13 /* ARM_SYSST bit shifts related to SoC reset sources */
19 /* Standardized reset source bits (across all OMAP SoCs) */
30 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
41 * omap1_get_reset_sources - return the source of the SoC's last reset
43 * Returns bits that represent the last reset source for the SoC. The
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/gpio/phosphor-gpio-monitor/
H A Dmulti-gpios-sys-init3 # shellcheck source=meta-facebook/recipes-fb/obmc_functions/files/fb-common-functions
4 source /usr/libexec/fb-common-functions
5 # shellcheck source=meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/power-cmd
6 source /usr/libexec/phosphor-state-manager/power-cmd
12 if [ "$(get_gpio "power-host-good")" -eq 1 ] && [ "$valid_sgpio" -eq 0 ]; then
13 systemctl start obmc-led-group-start@power_on.service
15 systemctl start obmc-led-group-stop@power_on.service
20 if [ "$(get_gpio post-end-n)" -eq 0 ]; then
21 busctl set-property xyz.openbmc_project.State.Host0 /xyz/openbmc_project/state/host0 \
25 busctl set-property xyz.openbmc_project.Software.Manager \
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/openbmc/linux/sound/soc/codecs/
H A Dcs35l56.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <sound/soc-dapm.h>
39 flush_work(&cs35l56->dsp_work); in cs35l56_wait_dsp_ready()
68 "ASP1 TX1 Source", "ASP1 TX2 Source", "ASP1 TX3 Source", "ASP1 TX4 Source"
73 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cs35l56->component); in cs35l56_sync_asp1_mixer_widgets_with_firmware()
74 const char *prefix = cs35l56->component->name_prefix; in cs35l56_sync_asp1_mixer_widgets_with_firmware()
82 if (cs35l56->asp1_mixer_widgets_initialized) in cs35l56_sync_asp1_mixer_widgets_with_firmware()
89 ret = pm_runtime_resume_and_get(cs35l56->base.dev); in cs35l56_sync_asp1_mixer_widgets_with_firmware()
96 ret = regmap_bulk_read(cs35l56->base.regmap, CS35L56_ASP1TX1_INPUT, in cs35l56_sync_asp1_mixer_widgets_with_firmware()
99 pm_runtime_mark_last_busy(cs35l56->base.dev); in cs35l56_sync_asp1_mixer_widgets_with_firmware()
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/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
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/openbmc/u-boot/arch/arm/dts/
H A Dast2600-u-boot.dtsi1 #include <dt-bindings/clock/ast2600-clock.h>
2 #include <dt-bindings/reset/ast2600-reset.h>
7 scu: clock-controller@1e6e2000 {
8 compatible = "aspeed,ast2600-scu";
10 u-boot,dm-pre-reloc;
11 #clock-cells = <1>;
12 #reset-cells = <1>;
13 uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
16 rst: reset-controller {
17 u-boot,dm-pre-reloc;
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/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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