1*f62d184eSSricharan Ramabadhran# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*f62d184eSSricharan Ramabadhran%YAML 1.2 3*f62d184eSSricharan Ramabadhran--- 4*f62d184eSSricharan Ramabadhran$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml# 5*f62d184eSSricharan Ramabadhran$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f62d184eSSricharan Ramabadhran 7*f62d184eSSricharan Ramabadhrantitle: Qualcomm Global Clock & Reset Controller on IPQ5018 8*f62d184eSSricharan Ramabadhran 9*f62d184eSSricharan Ramabadhranmaintainers: 10*f62d184eSSricharan Ramabadhran - Sricharan Ramabadhran <quic_srichara@quicinc.com> 11*f62d184eSSricharan Ramabadhran 12*f62d184eSSricharan Ramabadhrandescription: | 13*f62d184eSSricharan Ramabadhran Qualcomm global clock control module provides the clocks, resets and power 14*f62d184eSSricharan Ramabadhran domains on IPQ5018 15*f62d184eSSricharan Ramabadhran 16*f62d184eSSricharan Ramabadhran See also:: 17*f62d184eSSricharan Ramabadhran include/dt-bindings/clock/qcom,ipq5018-gcc.h 18*f62d184eSSricharan Ramabadhran include/dt-bindings/reset/qcom,ipq5018-gcc.h 19*f62d184eSSricharan Ramabadhran 20*f62d184eSSricharan Ramabadhranproperties: 21*f62d184eSSricharan Ramabadhran compatible: 22*f62d184eSSricharan Ramabadhran const: qcom,gcc-ipq5018 23*f62d184eSSricharan Ramabadhran 24*f62d184eSSricharan Ramabadhran clocks: 25*f62d184eSSricharan Ramabadhran items: 26*f62d184eSSricharan Ramabadhran - description: Board XO source 27*f62d184eSSricharan Ramabadhran - description: Sleep clock source 28*f62d184eSSricharan Ramabadhran - description: PCIE20 PHY0 pipe clock source 29*f62d184eSSricharan Ramabadhran - description: PCIE20 PHY1 pipe clock source 30*f62d184eSSricharan Ramabadhran - description: USB3 PHY pipe clock source 31*f62d184eSSricharan Ramabadhran - description: GEPHY RX clock source 32*f62d184eSSricharan Ramabadhran - description: GEPHY TX clock source 33*f62d184eSSricharan Ramabadhran - description: UNIPHY RX clock source 34*f62d184eSSricharan Ramabadhran - description: UNIPHY TX clk source 35*f62d184eSSricharan Ramabadhran 36*f62d184eSSricharan Ramabadhranrequired: 37*f62d184eSSricharan Ramabadhran - compatible 38*f62d184eSSricharan Ramabadhran - clocks 39*f62d184eSSricharan Ramabadhran 40*f62d184eSSricharan RamabadhranallOf: 41*f62d184eSSricharan Ramabadhran - $ref: qcom,gcc.yaml# 42*f62d184eSSricharan Ramabadhran 43*f62d184eSSricharan RamabadhranunevaluatedProperties: false 44*f62d184eSSricharan Ramabadhran 45*f62d184eSSricharan Ramabadhranexamples: 46*f62d184eSSricharan Ramabadhran - | 47*f62d184eSSricharan Ramabadhran clock-controller@1800000 { 48*f62d184eSSricharan Ramabadhran compatible = "qcom,gcc-ipq5018"; 49*f62d184eSSricharan Ramabadhran reg = <0x01800000 0x80000>; 50*f62d184eSSricharan Ramabadhran clocks = <&xo_board_clk>, 51*f62d184eSSricharan Ramabadhran <&sleep_clk>, 52*f62d184eSSricharan Ramabadhran <&pcie20_phy0_pipe_clk>, 53*f62d184eSSricharan Ramabadhran <&pcie20_phy1_pipe_clk>, 54*f62d184eSSricharan Ramabadhran <&usb3_phy0_pipe_clk>, 55*f62d184eSSricharan Ramabadhran <&gephy_rx_clk>, 56*f62d184eSSricharan Ramabadhran <&gephy_tx_clk>, 57*f62d184eSSricharan Ramabadhran <&uniphy_rx_clk>, 58*f62d184eSSricharan Ramabadhran <&uniphy_tx_clk>; 59*f62d184eSSricharan Ramabadhran #clock-cells = <1>; 60*f62d184eSSricharan Ramabadhran #reset-cells = <1>; 61*f62d184eSSricharan Ramabadhran #power-domain-cells = <1>; 62*f62d184eSSricharan Ramabadhran }; 63*f62d184eSSricharan Ramabadhran... 64