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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
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H A Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NX
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H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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H A Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
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/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
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/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Dsamsung,s6e8aa0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
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H A Dsamsung,ld9040.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
20 display-timings: true
23 reset-gpios: true
25 vdd3-supply:
28 vci-supply:
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/openbmc/linux/include/linux/reset/
H A Dreset-simple.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Simple Reset Controller ops
5 * Based on Allwinner SoCs Reset Controller driver
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
23 * @rcdev: reset controller device base structure
24 * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
25 * are set to assert the reset. Note that this says nothing about
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/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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/openbmc/phosphor-power/tools/power-utils/
H A Daei_updater.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
26 #include <phosphor-logging/lg2.hpp>
33 // Suppress clang-tidy errors for unused variables that are intended
37 #pragma clang diagnostic ignored "-Wunused-variable"
42 constexpr int ISP_STATUS_DELAY = 1200; // Delay for ISP status check (1.2s)
43 constexpr int MEM_WRITE_DELAY = 5000; // Memory write delay (5s)
44 constexpr int MEM_STRETCH_DELAY = 10; // Delay between writes (10ms)
45 constexpr int MEM_COMPLETE_DELAY = 2000; // Delay before completion (2s)
46 constexpr int REBOOT_DELAY = 8000; // Delay for reboot (8s)
63 constexpr uint8_t CMD_RESET_SEQ = 0x01; // This command will reset ISP OS for
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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/openbmc/u-boot/drivers/usb/host/
H A Dehci-omap.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2004-2008
20 #include <asm/ehci-omap.h>
33 rev = readl(&uhh->rev); in omap_uhh_reset()
35 /* Soft RESET */ in omap_uhh_reset()
36 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc); in omap_uhh_reset()
40 /* Wait for soft RESET to complete */ in omap_uhh_reset()
41 while (!(readl(&uhh->syss) & 0x1)) { in omap_uhh_reset()
43 printf("%s: RESET timeout\n", __func__); in omap_uhh_reset()
44 return -1; in omap_uhh_reset()
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/openbmc/u-boot/doc/
H A DREADME.bootmenu1 SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011-2012 Pali Rohár <pali.rohar@gmail.com>
8 The "bootmenu" command uses U-Boot menu interfaces and provides
13 menu entry invokes an U-Boot command (or a list of commands)
23 bootmenu_delay=<delay>
26 <delay> is the autoboot delay in seconds, after which the first
40 First (optional) argument of the "bootmenu" command is a delay specifier
41 and it overrides the delay value defined by "bootmenu_delay" environment
43 the argument of the "bootmenu" command is not specified, the default delay
44 will be CONFIG_BOOTDELAY. If delay is 0, no menu entries will be shown on
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/openbmc/linux/include/linux/dma/
H A Dxilinx_dma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 #include <linux/dma-mapping.h>
15 * struct xilinx_vdma_config - VDMA Configuration structure
16 * @frm_dly: Frame delay
17 * @gen_lock: Whether in gen-lock mode
23 * @delay: Delay counter
24 * @reset: Reset Channel
36 int delay; member
37 int reset; member
/openbmc/linux/drivers/scsi/qla4xxx/
H A Dql4_83xx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
169 flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1); in qla4_83xx_lockless_flash_read_u32()
188 (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra124-usb-phy
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/openbmc/phosphor-state-manager/
H A Ddiscover_system_state.cpp10 #include <systemd/sd-bus.h>
12 #include <phosphor-logging/elog-errors.hpp>
13 #include <phosphor-logging/lg2.hpp>
55 while ((arg = getopt_long(argc, argv, "h:", longOpts, &optIndex)) != -1) in main()
82 // If the BMC was rebooted due to a user initiated pinhole reset, do not in main()
96 "BMC was reset due to pinhole reset, no power restore policy will be run"); in main()
102 "BMC was reset due to cold reset, no power restore policy will be run"); in main()
106 /* The logic here is to first check the one-time PowerRestorePolicy setting. in main()
108 * user setting in the non one-time object, otherwise honor the one-time in main()
142 // one_time setting was set so we're going to use it. Reset it in main()
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/openbmc/linux/drivers/video/backlight/
H A Dlms283gf05.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * lms283gf05.c -- support for Samsung LMS283GF05 LCD
10 #include <linux/delay.h>
21 struct gpio_desc *reset; member
27 unsigned char delay; member
32 /* REG, VALUE, DELAY */
95 gpiod_set_value(gpiod, 0); /* De-asserted */ in lms283gf05_reset()
99 gpiod_set_value(gpiod, 0); /* De-asserted */ in lms283gf05_reset()
120 mdelay(seq[i].delay); in lms283gf05_toggle()
127 struct spi_device *spi = st->spi; in lms283gf05_power_set()
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/openbmc/linux/include/linux/usb/
H A Disp1362.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * board initialization code should put one of these into dev->platform_data
15 /* On-chip overcurrent protection */
33 /* Hardware reset set/clear */
34 void (*reset) (struct device *dev, int set); member
37 /* Inter-io delay (ns). The chip is picky about access timings; it
39 * 110ns delay between consecutive accesses to DATA_REG,
40 * 300ns delay between access to ADDR_REG and DATA_REG (registers)
41 * 462ns delay between access to ADDR_REG and DATA_REG (buffer memory)
44 void (*delay) (struct device *dev, unsigned int delay); member
/openbmc/u-boot/arch/arm/dts/
H A Dtegra124.dtsi1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
14 interrupt-parent = <&lic>;
17 pcie-controller@01003000 {
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/openbmc/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_init.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
11 /* Reset template definitions */
74 u16 delay; member
78 u16 delay;
125 "Need Reset",
136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); in qlcnic_83xx_idc_check_driver_presence_reg()
146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
149 dev_info(&adapter->pdev->dev, in qlcnic_83xx_idc_log_state_history()
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/openbmc/linux/drivers/input/misc/
H A Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
32 /* Regulator control registers for shutdown/reset */
52 /* Buck TEST2 registers for shutdown/reset */
71 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
107 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
117 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
130 bool reset = system_state == SYSTEM_RESTART; in pmic8xxx_pwrkey_shutdown() local
132 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
133 error = pwrkey->shutdown_fn(pwrkey, reset); in pmic8xxx_pwrkey_shutdown()
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/openbmc/linux/drivers/iio/imu/
H A Dadis.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/delay.h>
27 * __adis_write_reg() - write N bytes to register (unlocked version)
41 .tx_buf = adis->tx, in __adis_write_reg()
45 .delay.value = adis->data->write_delay, in __adis_write_reg()
46 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
47 .cs_change_delay.value = adis->data->cs_change_delay, in __adis_write_reg()
50 .tx_buf = adis->tx + 2, in __adis_write_reg()
54 .delay.value = adis->data->write_delay, in __adis_write_reg()
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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dnxp,lpc1850-rgu.txt1 NXP LPC1850 Reset Generation Unit (RGU)
4 Please also refer to reset.txt in this directory for common reset
8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
14 See table below for valid peripheral reset numbers. Numbers not
18 Reset Peripheral
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
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/openbmc/linux/drivers/reset/
H A Dreset-lpc18xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU).
9 #include <linux/delay.h>
16 #include <linux/reset-controller.h>
27 /* Internal reset outputs */
50 writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0); in lpc18xx_rgu_restart()
59 * The LPC18xx RGU has mostly self-deasserting resets except for the
60 * two reset lines going to the internal Cortex-M0 cores.
79 spin_lock_irqsave(&rc->lock, flags); in lpc18xx_rgu_setclear_reset()
80 stat = ~readl(rc->base + stat_offset); in lpc18xx_rgu_setclear_reset()
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