| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | mti,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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| /openbmc/linux/arch/ia64/include/asm/ |
| H A D | hw_irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * 1,3-14 are reserved from firmware
25 * 16-255 (vectored external interrupts) are available
37 #define AUTO_ASSIGN -1
42 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
45 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
47 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
49 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
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| /openbmc/linux/Documentation/devicetree/bindings/powerpc/ |
| H A D | ibm,powerpc-cpu-features.txt | 3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
12 This device tree binding describes CPU features available to software, with
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
24 Description: Container of CPU feature nodes.
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
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| /openbmc/qemu/hw/intc/ |
| H A D | armv7m_nvic.c | 4 * Copyright (c) 2006-2007 CodeSourcery.
20 #include "hw/qdev-properties.h"
23 #include "target/arm/cpu.h"
24 #include "target/arm/cpu-features.h"
25 #include "exec/exec-all.h"
33 * the num-irq property counts the number of external IRQ lines
44 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
56 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
58 /* Effective running priority of the CPU when no exception is active
62 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-mips-gic.c | 6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
35 /* Add 2 to convert GIC CPU pin to core interrupt */
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
105 irq -= GIC_PIN_TO_VEC_OFFSET; in gic_bind_eic_interrupt()
111 static void gic_send_ipi(struct irq_data *d, unsigned int cpu) in gic_send_ipi() argument
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| /openbmc/linux/arch/xtensa/include/asm/ |
| H A D | mmu_context.h | 8 * Copyright (C) 2001 - 2013 Tensilica Inc.
23 #include <asm/vectors.h>
27 #include <asm-generic/mm_hooks.h>
28 #include <asm-generic/percpu.h>
35 #define cpu_asid_cache(cpu) per_cpu(asid_cache, cpu) argument
39 * any user or kernel context. We use the reserved values in the
44 * 2 reserved
45 * 3 reserved
51 #define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
70 static inline void get_new_mmu_context(struct mm_struct *mm, unsigned int cpu) in get_new_mmu_context() argument
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| /openbmc/linux/arch/xtensa/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
58 Xtensa processors are 32-bit RISC machines designed by Tensilica
63 a home page at <http://www.linux-xtensa.org/>.
102 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
108 …def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null…
117 bool "fsf - default (not generic) configuration"
121 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
128 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
164 ie: it supports a TLB with auto-loading, page protection.
221 byte and 2-byte access to memory attached to instruction bus.
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| /openbmc/linux/kernel/irq/ |
| H A D | matrix.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/cpu.h>
43 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
62 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
63 m->alloc_start = alloc_start; in irq_alloc_matrix()
64 m->alloc_end = alloc_end; in irq_alloc_matrix()
65 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
66 m->maps = alloc_percpu(*m->maps); in irq_alloc_matrix()
67 if (!m->maps) { in irq_alloc_matrix()
75 * irq_matrix_online - Bring the local CPU matrix online
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| /openbmc/linux/arch/m68k/ |
| H A D | Kconfig.machine | 1 # SPDX-License-Identifier: GPL-2.0
23 This option enables support for the 68000-based Atari series of
41 browse the documentation available at <http://www.mac.linux-m68k.org/>;
50 Say Y here if you want to run Linux on an MC680x0-based Apollo
70 build a kernel which can run on MVME147 single-board computers. If
130 The Q40 is a Motorola 68040-based successor to the Sinclair QL
133 Q60. Select your CPU below. For 68LC060 don't forget to enable FPU
212 Disable the CPU internal registers protection in user mode,
306 Support for the Sysam AMCORE open-hardware generic board.
312 Support for the Sysam stmark2 open-hardware generic board.
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| /openbmc/linux/arch/x86/kernel/apic/ |
| H A D | vector.c | 1 // SPDX-License-Identifier: GPL-2.0-only
30 unsigned int cpu; member
78 info->mask = mask; in init_irq_alloc_info()
94 while (irqd->parent_data) in apic_chip_data()
95 irqd = irqd->parent_data; in apic_chip_data()
97 return irqd->chip_data; in apic_chip_data()
104 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
119 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
129 unsigned int cpu) in apic_update_irq_cfg() argument
135 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
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| /openbmc/linux/Documentation/filesystems/ |
| H A D | xfs-delayed-logging-design.rst | 1 .. SPDX-License-Identifier: GPL-2.0
33 details logged are made up of the changes to in-core structures rather than
34 on-disk structures. Other objects - typically buffers - have their physical
40 The reason for these differences is to keep the amount of log space and CPU time
64 place. This means that permanent transactions can be used for one-shot
65 modifications, but one-shot reservations cannot be used for permanent
68 In the code, a one-shot transaction pattern looks somewhat like this::
97 While this might look similar to a one-shot transaction, there is an important
123 the on-disk journal.
165 transaction, we have to reserve enough space to record a full leaf-to-root split
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| /openbmc/linux/arch/arc/kernel/ |
| H A D | entry-arcv2.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
17 ; first 16 lines are reserved for exceptions and are not configurable.
20 .cpu HS
29 # Initial 16 slots are Exception Vectors
44 VECTOR reserved ; Reserved slots
45 VECTOR reserved ; Reserved slots
47 # Begin Interrupt Vectors
58 .rept NR_CPU_IRQS - 8
64 reserved: label
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| /openbmc/linux/Documentation/arch/arm/ |
| H A D | memory.rst | 13 The ARM CPU is capable of addressing a maximum of 4GB virtual memory
30 ffff1000 ffff7fff Reserved.
33 ffff0000 ffff0fff CPU vector page.
34 The CPU vectors are mapped here if the
35 CPU supports vector relocation (control
39 in proc-xscale.S to flush the whole data
43 DTCM mounted inside the CPU.
46 ITCM mounted inside the CPU.
53 ff800000 ffbfffff Permanent, fixed read-only mapping of the
59 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
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| /openbmc/linux/arch/x86/include/asm/ |
| H A D | segment.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
16 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
61 * The layout of the per-CPU GDT under Linux:
63 * 0 - null <=== cacheline #1
64 * 1 - reserved
65 * 2 - reserved
66 * 3 - reserved
68 * 4 - unused <=== cacheline #2
69 * 5 - unused
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| /openbmc/linux/arch/arm64/kernel/ |
| H A D | proton-pack.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
12 * Copyright (C) 2018 ARM Ltd, All Rights Reserved.
20 #include <linux/arm-smccc.h>
22 #include <linux/cpu.h>
28 #include <asm/debug-monitors.h>
32 #include <asm/vectors.h>
37 * onlining a late CPU.
70 * This one sucks. A CPU is either:
72 * - Mitigated in hardware and advertised by ID_AA64PFR0_EL1.CSV2.
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| H A D | entry.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
29 #include <asm/asm-uaccess.h>
44 * skipped by the trampoline vectors, to trigger the cleanup.
64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
89 * after panic() re-enables interrupts.
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| /openbmc/u-boot/arch/mips/ |
| H A D | Kconfig | 16 bool "Support qemu-mips"
63 bool "Support MSCC VCore-III"
70 select CPU
150 source "board/qemu-mips/Kconfig"
151 source "arch/mips/mach-ath79/Kconfig"
152 source "arch/mips/mach-mscc/Kconfig"
153 source "arch/mips/mach-bmips/Kconfig"
154 source "arch/mips/mach-jz47xx/Kconfig"
155 source "arch/mips/mach-pic32/Kconfig"
156 source "arch/mips/mach-mt7620/Kconfig"
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| /openbmc/qemu/docs/specs/ |
| H A D | rocker.rst | 23 --------
30 -------------------------
36 * The use of RSVD or Reserved indicates that a bit or field is reserved for
39 * Register are (R) read-only, (R/W) read/write, (W) write-only, or (COR) clear
41 * TLV values in network-byte-order are designated with (N).
48 -----------------------
53 ---------------------------------------------
62 0xF 1 Built-in self test
65 0x18-28 Reserved
68 0x30-38 Reserved
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| /openbmc/linux/drivers/infiniband/hw/efa/ |
| H A D | efa_main.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 * Copyright 2018-2022 Amazon.com, Inc. or its affiliates. All rights reserved.
45 ibdev_err(&dev->ibdev, in unimplemented_aenq_handler()
53 atomic64_inc(&dev->stats.keep_alive_rcvd); in efa_keep_alive()
65 struct pci_dev *pdev = dev->pdev; in efa_release_bars()
74 u16 cqn = eqe->u.comp_event.cqn; in efa_process_comp_eqe()
78 cq = xa_load(&dev->cqs_xa, cqn); in efa_process_comp_eqe()
80 ibdev_err_ratelimited(&dev->ibdev, in efa_process_comp_eqe()
81 "Completion event on non-existent CQ[%u]", in efa_process_comp_eqe()
86 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); in efa_process_comp_eqe()
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | head_book3s_32.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
14 * This file contains the low-level support and setup for the
30 #include <asm/asm-offsets.h>
34 #include <asm/feature-fixups.h>
40 /* see the comment for clear_bats() -- Cort */ \
65 * -- Cort
77 * pointer (r1) points to just below the end of the half-meg region
78 * from 0x380000 - 0x400000, which is mapped in already.
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| /openbmc/u-boot/arch/arm/include/asm/arch-omap3/ |
| H A D | omap.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2008
5 * Richard Woodruff <r-woodruff2@ti.com>
27 * L4 Peripherals - L4 Wakeup and L4 Core now
142 /* base address for indirect vectors (internal boot mode) */
153 #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
157 /* scratch area - accessible on both EMU and GP */
166 #define DDR_COMBO 2 /* combo part on cpu daughter card */
169 #define DDR_100 100 /* type found on most mem d-boards */
171 #define DDR_133 133 /* most combo, some mem d-boards */
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| /openbmc/u-boot/arch/arm/cpu/armv7/ |
| H A D | nonsec_virt.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * code for switching cores into non-secure state and into HYP mode
12 #include <asm/proc-armv/ptrace.h>
39 * U-Boot calls this "software interrupt" in start.S
41 * to non-secure state.
104 movs pc, lr @ ERET to non-secure
119 bfc \addr, #0, #15 @ clear reserved bits
131 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
132 moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
139 * of the non-secure and HYP mode transition. The GIC distributor specific
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| /openbmc/qemu/target/xtensa/ |
| H A D | cpu.h | 3 * All rights reserved.
31 #include "cpu-qom.h"
32 #include "qemu/cpu-float.h"
33 #include "exec/cpu-defs.h"
35 #include "xtensa-isa.h"
218 ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \
244 /* Static vectors */
249 /* Dynamic vectors */
556 * An Xtensa CPU.
569 * @config: The CPU core configuration.
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * number used in the Programming Environments Manual For 32-Bit
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
74 /* so tests for these bits fail on 32-bit */
116 #define MSR_TS_N 0 /* Non-transactional */
120 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
161 /* Power Management - Processor Stop Status and Control Register Fields */
165 #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
169 #define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
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| /openbmc/linux/arch/arm64/kvm/hyp/include/nvhe/ |
| H A D | fixed_config.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * - Needed by common Linux distributions (e.g., floating point)
27 * - Trivial to support, e.g., supporting the feature does not introduce or
29 * - Cannot be trapped or prevent the guest from using anyway
34 * - Floating-point and Advanced SIMD
35 * - Data Independent Timing
36 * - Spectre/Meltdown Mitigation
48 * - AArch64 guests only (no support for AArch32 guests):
51 * - RAS (v1)
64 * - Branch Target Identification
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