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/openbmc/linux/drivers/clk/imx/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
115 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
127 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
[all …]
H A Dclk-busy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
16 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument
20 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait()
22 return -ETIMEDOUT; in clk_busy_wait()
30 void __iomem *reg; member
31 u8 shift; member
46 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); in clk_busy_divider_recalc_rate()
54 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); in clk_busy_divider_round_rate()
63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
13 reg = <0x4>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
13 reg = <0x78>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
27 reg = <0x78>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/memory/tegra/
H A Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
53 .reg = 0x228,
57 .reg = 0x2e8,
[all …]
H A Dtegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
20 .reg = 0x34c,
21 .shift = 0,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
48 .reg = 0x228,
52 .reg = 0x2f4,
53 .shift = 0,
[all …]
H A Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra124-mc.h>
21 .reg = 0x34c,
22 .shift = 0,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
49 .reg = 0x228,
53 .reg = 0x2f4,
54 .shift = 0,
[all …]
H A Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
42 .reg = 0x34c,
43 .shift = 0,
55 .reg = 0x228,
59 .reg = 0x2e8,
60 .shift = 0,
72 .reg = 0x228,
76 .reg = 0x2f4,
77 .shift = 0,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Domap3xxx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
21 reg = <0x0d40>;
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
28 ti,bit-shift = <6>;
29 ti,max-div = <3>;
[all …]
H A Ddra7xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
[all …]
H A Domap34xx-omap36xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <1>;
20 #clock-cells = <0>;
21 compatible = "ti,omap3-interface-clock";
23 ti,bit-shift = <3>;
24 reg = <0x0a14>;
28 #clock-cells = <0>;
29 compatible = "ti,omap3-interface-clock";
[all …]
H A Dam43xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
15 ti,bit-shift = <31>;
16 reg = <0x0040>;
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
23 ti,bit-shift = <29>;
24 reg = <0x0040>;
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
[all …]
/openbmc/qemu/target/i386/
H A Dops_sse.h22 #include "crypto/aes-round.h"
25 #if SHIFT == 0
26 #define Reg MMXReg macro
34 #define Reg ZMMReg macro
40 #if SHIFT == 1
47 #define LANE_WIDTH (SHIFT ? 16 : 8)
50 #if SHIFT == 0
51 #define FPSRL(x, c) ((x) >> shift)
52 #define FPSRAW(x, c) ((int16_t)(x) >> shift)
53 #define FPSRAL(x, c) ((int32_t)(x) >> shift)
[all …]
/openbmc/linux/drivers/bus/
H A Dda8xx-mstpri.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * some changes (as is the case for the LCD controller on da850-lcdk - the
54 int reg; member
55 int shift; member
61 .reg = DA8XX_MSTPRI0_OFFSET,
62 .shift = 0,
66 .reg = DA8XX_MSTPRI0_OFFSET,
67 .shift = 4,
71 .reg = DA8XX_MSTPRI0_OFFSET,
72 .shift = 16,
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
18 u32 reg; in scg_src_get_rate() local
22 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
23 if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) in scg_src_get_rate()
28 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
29 if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) in scg_src_get_rate()
34 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
35 if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) in scg_src_get_rate()
40 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dvp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * struct omap_vp_ops - per-VP operations
36 * struct omap_vp_common - register data common to all VDDs
37 * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
38 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
39 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
40 * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
41 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
42 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
43 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_meson.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 - BayLibre, SAS
14 unsigned int reg; member
20 .reg = (_reg), \
28 u8 shift; member
32 #define PMASK(width) GENMASK(width - 1, 0)
33 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
34 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
36 #define PARM_GET(width, shift, reg) \ argument
[all …]
/openbmc/linux/drivers/soc/aspeed/
H A Daspeed-uart-routing.c1 // SPDX-License-Identifier: GPL-2.0+
41 uint8_t reg; member
43 uint8_t shift; member
68 .reg = HICR9,
69 .shift = 8,
88 .reg = HICRA,
89 .shift = 28,
108 .reg = HICRA,
109 .shift = 25,
126 .reg = HICRA,
[all …]
/openbmc/linux/drivers/regulator/
H A Dmax8998.c1 // SPDX-License-Identifier: GPL-2.0+
3 // max8998.c - Voltage regulator driver for the Maxim 8998
5 // Copyright (C) 2009-2010 Samsung Electronics
23 #include <linux/mfd/max8998-private.h>
41 int *reg, int *shift) in max8998_get_enable_register() argument
47 *reg = MAX8998_REG_ONOFF1; in max8998_get_enable_register()
48 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
51 *reg = MAX8998_REG_ONOFF2; in max8998_get_enable_register()
52 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
55 *reg = MAX8998_REG_ONOFF3; in max8998_get_enable_register()
[all …]
/openbmc/qemu/target/i386/tcg/
H A Dops_sse_header.h.inc19 #if SHIFT == 0
20 #define Reg MMXReg
23 #define Reg ZMMReg
24 #if SHIFT == 1
34 #define dh_ctype_Reg Reg *
41 DEF_HELPER_4(glue(psrlw, SUFFIX), void, env, Reg, Reg, Reg)
42 DEF_HELPER_4(glue(psraw, SUFFIX), void, env, Reg, Reg, Reg)
43 DEF_HELPER_4(glue(psllw, SUFFIX), void, env, Reg, Reg, Reg)
44 DEF_HELPER_4(glue(psrld, SUFFIX), void, env, Reg, Reg, Reg)
45 DEF_HELPER_4(glue(psrad, SUFFIX), void, env, Reg, Reg, Reg)
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-axm5516.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22 * struct axxia_clk - Common struct to all Axxia clocks.
33 * struct axxia_pllclk - Axxia PLL generated clock.
35 * @reg: Offset into regmap for PLL control register
39 u32 reg; member
44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
[all …]
/openbmc/linux/drivers/clk/meson/
H A Dparm.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define PMASK(width) GENMASK(width - 1, 0)
14 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
15 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
17 #define PARM_GET(width, shift, reg) \ argument
18 (((reg) & SETPMASK(width, shift)) >> (shift))
19 #define PARM_SET(width, shift, reg, val) \ argument
20 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
22 #define MESON_PARM_APPLICABLE(p) (!!((p)->width))
26 u8 shift; member
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu_nkmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
39 for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) { in ccu_nkmp_find_best()
40 for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) { in ccu_nkmp_find_best()
41 for (_m = nkmp->min_m; _m <= nkmp->max_m; _m++) { in ccu_nkmp_find_best()
42 for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) { in ccu_nkmp_find_best()
52 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_nkmp_find_best()
64 nkmp->n = best_n; in ccu_nkmp_find_best()
65 nkmp->k = best_k; in ccu_nkmp_find_best()
[all …]

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