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/openbmc/qemu/gdb-xml/
H A Dhexagon-core.xml2 <!--
3 Copyright(c) 2023-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
7 top-level directory.
12 …https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-…
13 …ub.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process…
14 -->
16 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
19 …<reg name="r00" altname="r0" bitsize="32" offset="0" encoding="uint" format="hex" group="Thread …
20 …<reg name="r01" altname="r1" bitsize="32" offset="4" encoding="uint" format="hex" group="Thread …
21 …<reg name="r02" altname="r2" bitsize="32" offset="8" encoding="uint" format="hex" group="Thread …
[all …]
H A Dhexagon-hvx.xml2 <!--
7 top-level directory.
12 …https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-…
13 …ub.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process…
14 -->
16 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
59 …<reg name="v0" bitsize="1024" offset="256" encoding="vector" format="hex" group="HVX Vector Regi…
60 …<reg name="v1" bitsize="1024" offset="384" encoding="vector" format="hex" group="HVX Vector Regi…
61 …<reg name="v2" bitsize="1024" offset="512" encoding="vector" format="hex" group="HVX Vector Regi…
62 …<reg name="v3" bitsize="1024" offset="640" encoding="vector" format="hex" group="HVX Vector Regi…
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_osdep.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
22 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \ argument
23 (iowrite16_rep(base + offset, data, count))
25 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \ argument
26 (ioread16_rep(base + (offset << 1), data, count))
28 #define er32(reg) \ argument
29 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
30 ? E1000_##reg : E1000_82542_##reg)))
32 #define ew32(reg, value) \ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_translate_dcn10.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-palmas.c1 // SPDX-License-Identifier: GPL-2.0-only
26 static int palmas_gpio_get(struct gpio_chip *gc, unsigned offset) in palmas_gpio_get() argument
29 struct palmas *palmas = pg->palmas; in palmas_gpio_get()
32 unsigned int reg; in palmas_gpio_get() local
33 int gpio16 = (offset/8); in palmas_gpio_get()
35 offset %= 8; in palmas_gpio_get()
36 reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; in palmas_gpio_get()
38 ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); in palmas_gpio_get()
40 dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret); in palmas_gpio_get()
44 if (val & BIT(offset)) in palmas_gpio_get()
[all …]
H A Dgpio-pmic-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48 * struct sprd_pmic_eic - PMIC EIC controller
51 * @offset: the EIC controller's offset address of the PMIC.
52 * @reg: the array to cache the EIC registers.
59 u32 offset; member
60 u8 reg[CACHE_NR_REGS]; member
65 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_pmic_eic_update() argument
66 u16 reg, unsigned int val) in sprd_pmic_eic_update() argument
69 u32 shift = SPRD_PMIC_EIC_BIT(offset); in sprd_pmic_eic_update()
[all …]
H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
45 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
212 const enum aspeed_gpio_reg reg) in bank_reg() argument
214 switch (reg) { in bank_reg()
216 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
218 return gpio->base + bank->rdata_reg; in bank_reg()
220 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
222 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
[all …]
H A Dgpio-cs5535.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
17 #define DRV_NAME "cs5535-gpio"
21 * 31-29,23 : reserved (always mask out)
24 * 22-16 : LPC
44 * design pattern, see Documentation/driver-api/driver-model/design-patterns.rst
61 unsigned int reg) in errata_outl() argument
63 unsigned long addr = chip->base + 0x80 + reg; in errata_outl()
68 * non-selected bits; the recommended workaround is a in errata_outl()
69 * read-modify-write operation. in errata_outl()
[all …]
/openbmc/qemu/hw/misc/
H A Dtrace-events3 # allwinner-cpucfg.c
5 allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%…
6 allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x…
8 # allwinner-h3-dramc.c
11 allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 …
12 allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx6…
13 allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 …
14 allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx6…
15 allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 …
16 allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx6…
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_translate_dcn30.c27 * Pre-requisites: headers required by header of this unit
59 #undef REG
60 #define REG(reg_name)\ macro
71 uint32_t offset, in offset_to_id() argument
76 switch (offset) { in offset_to_id()
78 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
108 case REG(DC_GPIO_HPD_A): in offset_to_id()
134 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
135 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_translate_dcn20.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
66 uint32_t offset, in offset_to_id() argument
71 switch (offset) { in offset_to_id()
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_translate_dcn315.c54 #undef REG
55 #define REG(reg_name)\ macro
56 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 uint32_t offset, in offset_to_id() argument
71 switch (offset) { in offset_to_id()
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dgpio-uniphier.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016-2017 Socionext Inc.
15 #include <dt-bindings/gpio/uniphier-gpio.h>
27 unsigned int reg; in uniphier_gpio_bank_to_reg() local
29 reg = (bank + 1) * 8; in uniphier_gpio_bank_to_reg()
33 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. in uniphier_gpio_bank_to_reg()
35 if (reg >= UNIPHIER_GPIO_IRQ_EN) in uniphier_gpio_bank_to_reg()
36 reg += 0x10; in uniphier_gpio_bank_to_reg()
38 return reg; in uniphier_gpio_bank_to_reg()
41 static void uniphier_gpio_get_bank_and_mask(unsigned int offset, in uniphier_gpio_get_bank_and_mask() argument
[all …]
H A Dtegra186_gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2016, NVIDIA CORPORATION.
15 #include <dm/device-internal.h>
16 #include <dt-bindings/gpio/gpio.h>
21 uint32_t offset; member
34 static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg, in tegra186_gpio_reg() argument
37 struct tegra186_gpio_platdata *plat = dev->platdata; in tegra186_gpio_reg()
38 uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4; in tegra186_gpio_reg()
40 return &(plat->regs[index]); in tegra186_gpio_reg()
43 static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset, in tegra186_gpio_set_out() argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_translate_dcn32.c27 * Pre-requisites: headers required by header of this unit
52 #undef REG
53 #define REG(reg_name)\ macro
54 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
64 uint32_t offset, in offset_to_id() argument
69 switch (offset) { in offset_to_id()
71 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
98 case REG(DC_GPIO_HPD_A): in offset_to_id()
121 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
122 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_translate_dcn21.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
65 uint32_t offset, in offset_to_id() argument
70 switch (offset) { in offset_to_id()
72 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
106 case REG(DC_GPIO_HPD_A): in offset_to_id()
132 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
133 case REG(DC_GPIO_GENLK_A): in offset_to_id()
158 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/openbmc/linux/drivers/net/ethernet/mscc/
H A Docelot_io.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
13 int __ocelot_bulk_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, in __ocelot_bulk_read_ix() argument
14 u32 offset, void *buf, int count) in __ocelot_bulk_read_ix() argument
19 ocelot_reg_to_target_addr(ocelot, reg, &target, &addr); in __ocelot_bulk_read_ix()
22 return regmap_bulk_read(ocelot->targets[target], addr + offset, in __ocelot_bulk_read_ix()
27 u32 __ocelot_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, u32 offset) in __ocelot_read_ix() argument
32 ocelot_reg_to_target_addr(ocelot, reg, &target, &addr); in __ocelot_read_ix()
35 regmap_read(ocelot->targets[target], addr + offset, &val); in __ocelot_read_ix()
40 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, enum ocelot_reg reg, in __ocelot_write_ix() argument
41 u32 offset) in __ocelot_write_ix() argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp_cm.c36 #define REG(reg)\ macro
37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); in dpp2_set_degamma_pwl()
183 /* value stored in dbg reg will be 1 greater than mode we want */ in program_gamut_remap()
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
[all …]
/openbmc/qemu/hw/xen/
H A Dxen_pt_config_init.c6 * the COPYING file in the top-level directory.
20 #include "hw/xen/xen-legacy-backend.h"
29 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
53 if (d->vendor_id == PCI_VENDOR_ID_INTEL && in xen_pt_hide_dev_cap()
54 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) { in xen_pt_hide_dev_cap()
68 QLIST_FOREACH(entry, &s->reg_grps, entries) { in xen_pt_find_reg_grp()
70 if ((entry->base_offset <= address) in xen_pt_find_reg_grp()
71 && ((entry->base_offset + entry->size) > address)) { in xen_pt_find_reg_grp()
84 XenPTRegInfo *reg = NULL; in xen_pt_find_reg() local
88 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) { in xen_pt_find_reg()
[all …]
/openbmc/linux/io_uring/
H A Dtctx.c1 // SPDX-License-Identifier: GPL-2.0
22 mutex_lock(&ctx->uring_lock); in io_init_wq_offload()
23 hash = ctx->hash_map; in io_init_wq_offload()
27 mutex_unlock(&ctx->uring_lock); in io_init_wq_offload()
28 return ERR_PTR(-ENOMEM); in io_init_wq_offload()
30 refcount_set(&hash->refs, 1); in io_init_wq_offload()
31 init_waitqueue_head(&hash->wait); in io_init_wq_offload()
32 ctx->hash_map = hash; in io_init_wq_offload()
34 mutex_unlock(&ctx->uring_lock); in io_init_wq_offload()
42 concurrency = min(ctx->sq_entries, 4 * num_online_cpus()); in io_init_wq_offload()
[all …]
/openbmc/u-boot/drivers/rtc/
H A Di2c_rtc_emul.c1 // SPDX-License-Identifier: GPL-2.0+
11 * but also supports setting the time, using an offset from the current
13 * time-keeping. It does not change the system time.
31 * struct sandbox_i2c_rtc_plat_data - platform data for the RTC
34 * @offset: RTC offset from current system time
36 * @reg: Register values
40 long offset; member
42 u8 reg[REG_COUNT]; member
50 int offset) in sandbox_i2c_rtc_set_offset() argument
55 old_offset = plat->offset; in sandbox_i2c_rtc_set_offset()
[all …]
/openbmc/u-boot/drivers/pinctrl/meson/
H A Dpinctrl-meson.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
8 #include <dm/device-internal.h>
17 #include "pinctrl-meson.h"
27 return priv->data->num_groups; in meson_pinctrl_get_groups_count()
35 if (!priv->data->groups[selector].name) in meson_pinctrl_get_group_name()
38 return priv->data->groups[selector].name; in meson_pinctrl_get_group_name()
45 return priv->data->num_funcs; in meson_pinmux_get_functions_count()
53 return priv->data->funcs[selector].name; in meson_pinmux_get_function_name()
56 static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset, in meson_gpio_calc_reg_and_bit() argument
[all …]
/openbmc/qemu/hw/char/
H A Dexynos4210_uart.c26 #include "qemu/error-report.h"
29 #include "chardev/char-fe.h"
30 #include "chardev/char-serial.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/qdev-properties-system.h"
64 * 'reg' - register offset (see offsets definitions above)
67 #define I_(reg) (reg / sizeof(uint32_t)) argument
71 hwaddr offset; member
150 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; member
167 static const char *exynos4210_uart_regname(hwaddr offset) in exynos4210_uart_regname() argument
[all …]
/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream()
43 u32 reg, maxval; in socfpga_a10_clk_get_upstream() local
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
54 dev_err(clk->dev, "Invalid control register\n"); in socfpga_a10_clk_get_upstream()
55 return -EINVAL; in socfpga_a10_clk_get_upstream()
[all …]

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