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/openbmc/qemu/gdb-xml/
H A Dhexagon-core.xml2 <!--
3 Copyright(c) 2023-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
7 top-level directory.
12 …https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-…
13 …ub.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process…
14 -->
16 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
19 …<reg name="r00" altname="r0" bitsize="32" offset="0" encoding="uint" format="hex" group="Thread …
20 …<reg name="r01" altname="r1" bitsize="32" offset="4" encoding="uint" format="hex" group="Thread …
21 …<reg name="r02" altname="r2" bitsize="32" offset="8" encoding="uint" format="hex" group="Thread …
[all …]
H A Dhexagon-hvx.xml2 <!--
7 top-level directory.
12 …https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-…
13 …ub.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process…
14 -->
16 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
59 …<reg name="v0" bitsize="1024" offset="256" encoding="vector" format="hex" group="HVX Vector Regi…
60 …<reg name="v1" bitsize="1024" offset="384" encoding="vector" format="hex" group="HVX Vector Regi…
61 …<reg name="v2" bitsize="1024" offset="512" encoding="vector" format="hex" group="HVX Vector Regi…
62 …<reg name="v3" bitsize="1024" offset="640" encoding="vector" format="hex" group="HVX Vector Regi…
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dgpio-uniphier.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016-2017 Socionext Inc.
15 #include <dt-bindings/gpio/uniphier-gpio.h>
27 unsigned int reg; in uniphier_gpio_bank_to_reg() local
29 reg = (bank + 1) * 8; in uniphier_gpio_bank_to_reg()
33 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. in uniphier_gpio_bank_to_reg()
35 if (reg >= UNIPHIER_GPIO_IRQ_EN) in uniphier_gpio_bank_to_reg()
36 reg += 0x10; in uniphier_gpio_bank_to_reg()
38 return reg; in uniphier_gpio_bank_to_reg()
41 static void uniphier_gpio_get_bank_and_mask(unsigned int offset, in uniphier_gpio_get_bank_and_mask() argument
[all …]
H A Dtegra186_gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2016, NVIDIA CORPORATION.
15 #include <dm/device-internal.h>
16 #include <dt-bindings/gpio/gpio.h>
21 uint32_t offset; member
34 static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg, in tegra186_gpio_reg() argument
37 struct tegra186_gpio_platdata *plat = dev->platdata; in tegra186_gpio_reg()
38 uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4; in tegra186_gpio_reg()
40 return &(plat->regs[index]); in tegra186_gpio_reg()
43 static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset, in tegra186_gpio_set_out() argument
[all …]
H A Dpm8916_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Qualcomm pm8916 pmic gpio driver - part of Qualcomm PM8916 PMIC
16 /* Register offset for each gpio */
53 static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset, in pm8916_gpio_set_direction() argument
57 uint32_t gpio_base = priv->pid + REG_OFFSET(offset); in pm8916_gpio_set_direction()
61 ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, in pm8916_gpio_set_direction()
68 ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, in pm8916_gpio_set_direction()
71 ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, in pm8916_gpio_set_direction()
77 ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL, in pm8916_gpio_set_direction()
84 /* Select the VIN - VIN0, pin is input so it doesn't matter */ in pm8916_gpio_set_direction()
[all …]
/openbmc/qemu/hw/misc/
H A Dtrace-events3 # allwinner-cpucfg.c
5 allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%…
6 allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x…
8 # allwinner-h3-dramc.c
11 allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 …
12 allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx6…
13 allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 …
14 allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx6…
15 allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 …
16 allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx6…
[all …]
H A Dimx25_ccm.c5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
8 * See the COPYING file in the top-level directory.
32 static const char *imx25_ccm_reg_name(uint32_t reg) in imx25_ccm_reg_name() argument
36 switch (reg) { in imx25_ccm_reg_name()
94 snprintf(unknown, sizeof(unknown), "[%u ?]", reg); in imx25_ccm_reg_name()
105 VMSTATE_UINT32_ARRAY(reg, IMX25CCMState, IMX25_CCM_MAX_REG),
115 if (EXTRACT(s->reg[IMX25_CCM_CCTL_REG], MPLL_BYPASS)) { in imx25_ccm_get_mpll_clk()
118 freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ); in imx25_ccm_get_mpll_clk()
133 if (EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_SRC)) { in imx25_ccm_get_mcu_clk()
137 freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV)); in imx25_ccm_get_mcu_clk()
[all …]
H A Dimx31_ccm.c5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
8 * See the COPYING file in the top-level directory.
34 static const char *imx31_ccm_reg_name(uint32_t reg) in imx31_ccm_reg_name() argument
38 switch (reg) { in imx31_ccm_reg_name()
92 snprintf(unknown, sizeof(unknown), "[%u ?]", reg); in imx31_ccm_reg_name()
102 VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
112 if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) { in imx31_ccm_get_pll_ref_clk()
113 if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) { in imx31_ccm_get_pll_ref_clk()
115 if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) { in imx31_ccm_get_pll_ref_clk()
133 freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG], in imx31_ccm_get_mpll_clk()
[all …]
H A Daspeed_scu.c9 * the COPYING file in the top-level directory.
14 #include "hw/qdev-properties.h"
20 #include "qemu/guest-random.h"
23 #include "target/arm/arm-powerctl.h"
25 #define TO_REG(offset) ((offset) >> 2) argument
286 return ASPEED_SCU_GET_CLASS(s)->get_apb(s); in aspeed_scu_get_apb_freq()
292 uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]); in aspeed_2400_scu_get_apb_freq()
294 return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) in aspeed_2400_scu_get_apb_freq()
295 / asc->apb_divider; in aspeed_2400_scu_get_apb_freq()
301 uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]); in aspeed_2600_scu_get_apb_freq()
[all …]
/openbmc/u-boot/drivers/rtc/
H A Di2c_rtc_emul.c1 // SPDX-License-Identifier: GPL-2.0+
11 * but also supports setting the time, using an offset from the current
13 * time-keeping. It does not change the system time.
31 * struct sandbox_i2c_rtc_plat_data - platform data for the RTC
34 * @offset: RTC offset from current system time
36 * @reg: Register values
40 long offset; member
42 u8 reg[REG_COUNT]; member
50 int offset) in sandbox_i2c_rtc_set_offset() argument
55 old_offset = plat->offset; in sandbox_i2c_rtc_set_offset()
[all …]
/openbmc/u-boot/board/freescale/common/
H A Dpfuze.c1 // SPDX-License-Identifier: GPL-2.0+
14 unsigned char offset, i, switch_num; in pfuze_mode_init() local
23 offset = PFUZE100_SW1CMODE; in pfuze_mode_init()
26 offset = PFUZE100_SW2MODE; in pfuze_mode_init()
29 return -EINVAL; in pfuze_mode_init()
38 for (i = 0; i < switch_num - 1; i++) { in pfuze_mode_init()
39 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); in pfuze_mode_init()
42 offset + i * SWITCH_SIZE); in pfuze_mode_init()
54 unsigned int reg; in pfuze_common_init() local
65 pmic_reg_read(p, PFUZE100_DEVICEID, &reg); in pfuze_common_init()
[all …]
/openbmc/u-boot/drivers/pinctrl/meson/
H A Dpinctrl-meson.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
8 #include <dm/device-internal.h>
17 #include "pinctrl-meson.h"
27 return priv->data->num_groups; in meson_pinctrl_get_groups_count()
35 if (!priv->data->groups[selector].name) in meson_pinctrl_get_group_name()
38 return priv->data->groups[selector].name; in meson_pinctrl_get_group_name()
45 return priv->data->num_funcs; in meson_pinmux_get_functions_count()
53 return priv->data->funcs[selector].name; in meson_pinmux_get_function_name()
56 static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset, in meson_gpio_calc_reg_and_bit() argument
[all …]
/openbmc/qemu/hw/char/
H A Dexynos4210_uart.c26 #include "qemu/error-report.h"
29 #include "chardev/char-fe.h"
30 #include "chardev/char-serial.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/qdev-properties-system.h"
64 * 'reg' - register offset (see offsets definitions above)
67 #define I_(reg) (reg / sizeof(uint32_t)) argument
71 hwaddr offset; member
150 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; member
167 static const char *exynos4210_uart_regname(hwaddr offset) in exynos4210_uart_regname() argument
[all …]
/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream()
43 u32 reg, maxval; in socfpga_a10_clk_get_upstream() local
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
54 dev_err(clk->dev, "Invalid control register\n"); in socfpga_a10_clk_get_upstream()
55 return -EINVAL; in socfpga_a10_clk_get_upstream()
[all …]
/openbmc/qemu/hw/xen/
H A Dxen_pt_config_init.c6 * the COPYING file in the top-level directory.
20 #include "hw/xen/xen-legacy-backend.h"
29 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
53 if (d->vendor_id == PCI_VENDOR_ID_INTEL && in xen_pt_hide_dev_cap()
54 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) { in xen_pt_hide_dev_cap()
68 QLIST_FOREACH(entry, &s->reg_grps, entries) { in xen_pt_find_reg_grp()
70 if ((entry->base_offset <= address) in xen_pt_find_reg_grp()
71 && ((entry->base_offset + entry->size) > address)) { in xen_pt_find_reg_grp()
84 XenPTRegInfo *reg = NULL; in xen_pt_find_reg() local
88 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) { in xen_pt_find_reg()
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv3_kvm.c2 * ARM Generic Interrupt Controller using KVM in-kernel support
26 #include "qemu/error-report.h"
47 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3"
89 kvm_arm_gic_set_irq(s->num_irq, irq, level); in kvm_arm_gicv3_set_irq()
92 #define KVM_VGIC_ATTR(reg, typer) \ argument
93 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
95 static inline void kvm_gicd_access(GICv3State *s, int offset, in kvm_gicd_access() argument
98 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, in kvm_gicd_access()
99 KVM_VGIC_ATTR(offset, 0), in kvm_gicd_access()
103 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, in kvm_gicr_access() argument
[all …]
H A Daspeed_intc.c6 * SPDX-License-Identifier: GPL-2.0-or-later
20 * values below are offset by - 0x1000 from datasheet
48 * values below are offset by - 0x100 from datasheet
155 uint32_t reg) in aspeed_intc_get_irq() argument
159 for (i = 0; i < aic->irq_table_count; i++) { in aspeed_intc_get_irq()
160 if (aic->irq_table[i].enable_reg == reg || in aspeed_intc_get_irq()
161 aic->irq_table[i].status_reg == reg) { in aspeed_intc_get_irq()
162 return &aic->irq_table[i]; in aspeed_intc_get_irq()
167 * Invalid reg. in aspeed_intc_get_irq()
184 assert((outpin_idx < aic->num_outpins) && (inpin_idx < aic->num_inpins)); in aspeed_intc_update()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
24 #include <asm/arch-fsl-layerscape/soc.h>
31 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) in fdt_fixup_phy_connection() argument
33 return fdt_setprop_string(blob, offset, "phy-connection-type", in fdt_fixup_phy_connection()
42 fdt32_t *reg; in ft_fixup_cpu() local
47 int off_prev = -1; in ft_fixup_cpu()
59 while (off != -FDT_ERR_NOTFOUND) { in ft_fixup_cpu()
60 reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); in ft_fixup_cpu()
61 if (reg) { in ft_fixup_cpu()
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Darmv7m.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 uint32_t vtor; /* Vector Table Offset Register */
31 uint32_t scr; /* offset 0x10: System Control Register */
32 uint32_t ccr; /* offset 0x14: Config and Control Register */
33 uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
34 uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
35 uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
36 uint32_t shcrs; /* offset 0x24: System Handler Control State */
37 uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */
38 uint32_t hfsr; /* offset 0x2C: HardFault Status Register */
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpci-aardvark.c20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
31 #include <asm-generic/gpio.h>
121 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) argument
135 * struct pcie_advk - Advk PCIe controller state
139 * first_busno stores the bus number of the PCIe root-port
150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) in advk_writel() argument
152 writel(val, pcie->base + reg); in advk_writel()
155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg) in advk_readl() argument
157 return readl(pcie->base + reg); in advk_readl()
161 * pcie_advk_addr_valid() - Check for valid bus address
[all …]
/openbmc/u-boot/drivers/net/phy/
H A Db53.c1 // SPDX-License-Identifier: GPL-2.0+
32 /* Pseudo-PHY address (non configurable) to access internal registers */
118 static int b53_mdio_op(struct mii_dev *bus, u8 page, u8 reg, u16 op) in b53_mdio_op() argument
126 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
132 v = (reg << 8) | op; in b53_mdio_op()
133 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
140 v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
149 return -EIO; in b53_mdio_op()
154 static int b53_mdio_read8(struct mii_dev *bus, u8 page, u8 reg, u8 *val) in b53_mdio_read8() argument
158 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ); in b53_mdio_read8()
[all …]
/openbmc/u-boot/board/freescale/ls1088a/
H A Dls1088a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
16 #include <fsl-mc/fsl_mc.h>
18 #include <asm/arch-fsl-layerscape/soc.h>
137 regs_info->regs = ifc_cfg_qspi_nor_boot; in ifc_cfg_boot_info()
139 regs_info->regs = ifc_cfg_ifc_nor_boot; in ifc_cfg_boot_info()
141 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; in ifc_cfg_boot_info()
160 if (gd->flags & GD_FLG_RELOC) in get_qixis_addr()
198 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); in fixup_ls1088ardb_pb_banner()
216 printf("Board: LS1088A-QDS, "); in checkboard()
[all …]
/openbmc/u-boot/drivers/axi/
H A Daxi-emul-uclass.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dm/device-internal.h>
17 u32 reg[2]; in axi_sandbox_get_emul() local
18 uint offset; in axi_sandbox_get_emul() local
22 offset = 1; in axi_sandbox_get_emul()
25 offset = 2; in axi_sandbox_get_emul()
28 offset = 4; in axi_sandbox_get_emul()
31 debug("%s: Unknown AXI transfer size '%d'", bus->name, size); in axi_sandbox_get_emul()
32 offset = 0; in axi_sandbox_get_emul()
37 * as-needed below. in axi_sandbox_get_emul()
[all …]
/openbmc/qemu/hw/timer/
H A Dbcm2835_systmr.c4 * Copyright (C) 2019 Philippe Mathieu-Daudé <f4bug@amsat.org>
6 * SPDX-License-Identifier: GPL-2.0-or-later
8 * Datasheet: BCM2835 ARM Peripherals (C6357-M-1398)
9 * https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
11 * Only the free running 64-bit counter is implemented.
35 trace_bcm2835_systmr_timer_expired(tmr->id); in bcm2835_systmr_timer_expire()
36 tmr->state->reg.ctrl_status |= 1 << tmr->id; in bcm2835_systmr_timer_expire()
37 qemu_set_irq(tmr->irq, 1); in bcm2835_systmr_timer_expire()
40 static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset, in bcm2835_systmr_read() argument
46 switch (offset) { in bcm2835_systmr_read()
[all …]
/openbmc/u-boot/include/dm/
H A Dfdtaddr.h1 /* SPDX-License-Identifier: GPL-2.0+ */
18 * devfdt_get_addr() - Get the reg property of a device
27 * devfdt_get_addr_ptr() - Return pointer to the address of the reg property
37 * devfdt_remap_addr() - Return pointer to the memory-mapped I/O address
38 * of the reg property of a device
47 * devfdt_remap_addr_index() - Return indexed pointer to the memory-mapped
48 * I/O address of the reg property of a device
49 * @index: the 'reg' property can hold a list of <addr, size> pairs
59 * devfdt_remap_addr_name() - Get the reg property of a device, indexed by
60 * name, as a memory-mapped I/O pointer
[all …]

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