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12

/openbmc/phosphor-dbus-interfaces/yaml/org/freedesktop/UPower/
H A DDevice.interface.yaml2 "org.freedesktop.UPower.Device -- Device interface
10 - name: Refresh
12 "Refreshes the data collected from the power source. Callers need the
13 org.freedesktop.upower.refresh-power-source authorization"
15 - name: GetHistory
17 "Gets history for the power device that is persistent across
20 - name: type
24 - name: timespan
28 - name: resolution
35 - name: data
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/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
26 * MPU CLOCK source before PLL
35 /* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
75 * 2=4096 3=8192 refresh
77 #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
90 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
91 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
94 * refresh to command)
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/openbmc/u-boot/board/ge/mx53ppd/
H A Dmx53ppd_video.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/iomux-mx53.h>
18 #include <asm/arch/imx-regs.h>
26 .name = "NV-SPWGRGB888",
27 .refresh = 60,
82 /* Set LDB_DI0 as clock source for IPU_DI0 */ in lcd_enable()
83 clrsetbits_le32(&mxc_ccm->cscmr2, in lcd_enable()
89 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3)); in lcd_enable()
92 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3)); in lcd_enable()
98 &iomux->gpr[2]); in lcd_enable()
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/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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/openbmc/webui-vue/src/locales/
H A Den-US.json18 "refresh": "Refresh", string
95 "power": "Power", string
97 "refresh": "Refresh", string
102 "titleRefresh": "Refresh application data"
134 "power": "@:appPageTitle.power", string
139 "power": "Power", string
155 "powerRestorePolicy": "Power restore policy",
161 "serverPowerOperations": "Server power operations",
206 "label": "24-hour time",
253 …"successStartBmcDump": "The dump will take some time to complete. Refresh the application to see t…
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/openbmc/u-boot/board/aristainetos/
H A Daristainetos.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/mx6-pins.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/video.h>
62 #include "./aristainetos-v1.c"
64 #include "./aristainetos-v2.c"
105 gd->ram_size = imx_ddr_size(); in dram_init()
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H A Daristainetos-v2.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/mx6-pins.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/video.h>
128 /* RST_LOC# PHY reset input (has pull-down!)*/
147 /* H1 Power enable = GPIO1_0*/
149 /* OTG Power enable = GPIO4_15*/
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/openbmc/u-boot/board/advantech/dms-ba16/
H A Ddms-ba16.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/mx6-pins.h>
14 #include <asm/mach-imx/mxc_i2c.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/video.h>
63 gd->ram_size = imx_ddr_size(); in dram_init()
199 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; in board_spi_cs_gpio()
236 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; in board_mmc_getcd()
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/openbmc/u-boot/board/ge/bx50v3/
H A Dbx50v3.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/mx6-pins.h>
14 #include <asm/mach-imx/mxc_i2c.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/video.h>
71 gd->ram_size = imx_ddr_size(); in dram_init()
207 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; in board_spi_cs_gpio()
244 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; in board_mmc_getcd()
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/openbmc/u-boot/arch/arm/mach-davinci/
H A Dda850_lowlevel.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SoC-specific lowlevel code for DA850
16 #include <asm/ti-common/davinci_nand.h>
40 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK); in da850_pll_init()
46 clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC); in da850_pll_init()
48 clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC); in da850_pll_init()
51 clrbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
60 dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9); in da850_pll_init()
61 setbits_le32(&reg->pllctl, in da850_pll_init()
66 clrbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
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/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5227x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
135 #define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
151 #define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
153 #define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
154 #define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
158 #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
162 #define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
163 #define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
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H A Dm5445x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
138 #define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */
143 #define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */
170 #define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */
217 #define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
218 #define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
219 #define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
220 #define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
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/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
224 #define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */
228 #define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */
232 #define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015
10 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
26 * Allwinner as part of the open-source bootloader release (refer to
27 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
36 * Note that the Zynq-documentation provides a very close match for the DDR
42 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
48 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
50 * 2) Only 2T-mode has been implemented and tested.
62 * The driver should be driven from a device-tree based configuration that
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H A Ddram_sun4i.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
8 * and earlier U-Boot Allwinner A10 SPL work
10 * (C) Copyright 2007-2012
68 writel(0, &timer->cpu_cfg); in mctl_ddr3_reset()
69 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
81 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
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H A Ddram_sunxi_dw.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015 Allwinner Technology Co.
23 writel(val | PIR_INIT, &mctl_ctl->pir); in mctl_phy_init()
24 mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); in mctl_phy_init()
33 clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
37 writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) | in mctl_set_bit_delays()
38 DXBDLR_READ_DELAY(para->dx_read_delays[i][j]), in mctl_set_bit_delays()
39 &mctl_ctl->dx[i].bdlr[j]); in mctl_set_bit_delays()
42 writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]), in mctl_set_bit_delays()
43 &mctl_ctl->acbdlr[i]); in mctl_set_bit_delays()
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/openbmc/openbmc/meta-openembedded/meta-xfce/recipes-panel-plugins/weather/xfce4-weather-plugin/
H A D0003-libsoup-Port-to-libsoup-3.0.patch2 From: =?UTF-8?q?=C4=90o=C3=A0n=20Tr=E1=BA=A7n=20C=C3=B4ng=20Danh?=
5 Subject: [PATCH 3/5] libsoup: Port to libsoup-3.0
7 Upstream-Status: Backport [https://github.com/xfce-mirror/xfce4-weather-plugin/commit/05b3ab7c755d7…
8 Signed-off-by: Khem Raj <raj.khem@gmail.com>
9 ---
10 README | 4 +-
11 configure.ac | 2 +-
12 panel-plugin/weather-config.c | 32 ++++---
13 panel-plugin/weather-search.c | 37 ++++++---
14 panel-plugin/weather-summary.c | 23 ++++--
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H A D0005-Make-libsoup-v3-support-optional.patch6 The plugin still targets Xfce4.16 and its contemporary is libsoup-2.4.
7 This commit is to be reverted when support for libsoup-2.4 is
10 Upstream-Status: Submitted [Upstream-Status: Backport [https://github.com/xfce-mirror/xfce4-weather…
11 Signed-off-by: Khem Raj <raj.khem@gmail.com>
12 ---
13 configure.ac | 5 +-
14 panel-plugin/weather-config.c | 28 +++++++
15 panel-plugin/weather-search.c | 32 ++++++++
16 panel-plugin/weather-summary.c | 21 +++++
17 panel-plugin/weather.c | 140 ++++++++++++++++++++++++++++++++-
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/openbmc/u-boot/arch/arm/dts/
H A Drk3288-veyron.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Google Veyron (and derivatives) board device tree source
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
18 stdout-path = &uart2;
22 u-boot,dm-pre-reloc;
23 u-boot,boot0 = &spi_flash;
28 pinctrl-names = "default";
29 pinctrl-0 = <&fw_wp_ap>;
30 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
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/openbmc/u-boot/drivers/ddr/fsl/
H A Dinteractive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
140 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); in fsl_ddr_spd_edit()
145 sizeof((common_timing_params_t *)0)->x, 0}
152 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; in lowest_common_dimm_parameters_edit()
210 sizeof((dimm_params_t *)0)->x, 0}
212 sizeof((dimm_params_t *)0)->x, 1}
220 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); in fsl_ddr_dimm_parameters_edit()
410 if (pdimm->n_ranks == 0) { in print_dimm_parameters()
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H A Dctrl_regs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
174 if (!popts->memctl_interleaving) in set_csn_config()
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/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dimx-regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Based on arch-mx31/imx-regs.h
9 * and arch-mx27/imx-regs.h
43 u32 pcmr0; /* Power Management Control 0 */
44 u32 pcmr1; /* Power Management Control 1 */
45 u32 pcmr2; /* Power Management Control 2 */
47 u32 lpimr0; /* Low Power Interrupt Mask 0 */
48 u32 lpimr1; /* Low Power Interrupt Mask 1 */
73 u32 cmp[3]; /* output compare 1-3 */
74 u32 capt[2]; /* input capture 1-2 */
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/openbmc/qemu/include/standard-headers/linux/
H A Dinput-event-codes.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
6 * This file is not only included from C-code but also from devicetree source
9 * Copyright (c) 1999-2002 Vojtech Pavlik
70 * AC - Application Control
71 * AL - Application Launch Button
72 * SC - System Control
191 #define KEY_POWER 116 /* SC System Power Down */
253 #define KEY_REFRESH 173 /* AC Refresh */
307 outputs (Monitor/LCD/TV-out/etc) */
326 #define KEY_VIDEO_NEXT 241 /* drive next video source */
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/openbmc/u-boot/include/dt-bindings/input/
H A Dlinux-event-codes.h5 * This file is not only included from C-code but also from devicetree source
8 * Copyright (c) 1999-2002 Vojtech Pavlik
69 * AC - Application Control
70 * AL - Application Launch Button
71 * SC - System Control
190 #define KEY_POWER 116 /* SC System Power Down */
252 #define KEY_REFRESH 173 /* AC Refresh */
305 outputs (Monitor/LCD/TV-out/etc) */
324 #define KEY_VIDEO_NEXT 241 /* drive next video source */
325 #define KEY_VIDEO_PREV 242 /* drive previous video source */
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/openbmc/u-boot/
H A DREADME1 # SPDX-License-Identifier: GPL-2.0+
3 # (C) Copyright 2000 - 2013
9 This directory contains the source code for U-Boot, a boot loader for
15 The development of U-Boot is closely related to Linux: some parts of
16 the source code originate in the Linux source tree, we have some
37 scattered throughout the U-Boot source identifying the people or
41 actual U-Boot source tree; however, it can be created dynamically
51 U-Boot, you should send a message to the U-Boot mailing list at
52 <u-boot@lists.denx.de>. There is also an archive of previous traffic
53 on the mailing list - please search the archive before asking FAQ's.
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