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/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-lpc32xx/pm.c
5 * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
12 * LPC32XX CPU and system power management
14 * The LPC32XX has three CPU modes for controlling system power: run,
15 * direct-run, and halt modes. When switching between halt and run modes,
16 * the CPU transistions through direct-run mode. For Linux, direct-run
25 * Direct-run mode:
28 * source or the frequency of the main oscillator. In this mode, the
36 * wake the system up back into direct-run mode.
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/openbmc/linux/arch/arm/mach-at91/
H A Dpm_suspend.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
16 .arch armv7-a
28 * Wait until master clock is ready (after switching master clock source)
91 * Set state for 2.5V low power regulator
92 * @ena: 0 - disable regulator
93 * 1 - enable regulator
125 * Enable self-refresh
164 /* Switch to self-refresh. */
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H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
35 * struct at91_pm_bu - AT91 power management backup unit data structure
52 * struct at91_pm_sfrbu_regs - registers mapping for SFRBU
53 * @pswbu: power switch BU control registers
65 * enum at91_pm_eth_clk - Ethernet clock indexes
77 * enum at91_pm_eth - Ethernet controller indexes
89 * struct at91_pm_quirk_eth - AT91 PM Ethernet quirks
93 * @modes: power management mode that this quirk applies to
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/openbmc/linux/include/soc/at91/
H A Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
22 #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
68 #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "F…
69 #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "…
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/openbmc/phosphor-dbus-interfaces/yaml/org/freedesktop/UPower/
H A DDevice.interface.yaml2 "org.freedesktop.UPower.Device -- Device interface
10 - name: Refresh
12 "Refreshes the data collected from the power source. Callers need the
13 org.freedesktop.upower.refresh-power-source authorization"
15 - name: GetHistory
17 "Gets history for the power device that is persistent across
20 - name: type
24 - name: timespan
28 - name: resolution
35 - name: data
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/openbmc/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
54 the DRAM refresh rate. This can be used as an indirect indicator
55 for the DRAM's temperature. Slower refresh rate means cooler RAM,
56 higher refresh rate means hotter RAM.
64 controller and specifically control the Self Refresh Power Down
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
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/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
26 * MPU CLOCK source before PLL
35 /* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
75 * 2=4096 3=8192 refresh
77 #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
90 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
91 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
94 * refresh to command)
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/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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/openbmc/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
81 .arch armv7-a
192 * Puts the current CPU in wait-for-event mode on the flow controller
193 * and powergates it -- flags (in R0) indicate the request type.
196 * corrupts r0-r4, r10-r12
215 * Clear this CPU's "event" and "interrupt" flags and power gate
260 wfeeq @ CPU should be power gated here
293 * CPU power-gating process, to avoid loading from SDRAM which
294 * are not supported once SDRAM is put into self-refresh.
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
60 * (access to non-DC registers will hang FPGA) */
146 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
148 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
229 /* note: part of refresh rate flag*/
247 /* Refresh rate divider when Miracast sink is using a
249 Must be zero for wired displays and non-zero for
318 /* Vertical refresh rate for progressive modes.
342 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
414 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
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/openbmc/linux/arch/arm/mach-imx/
H A Dsuspend-imx6.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-offsets.h>
9 #include <asm/hardware/cache-l2x0.h>
12 .arch armv7-a
38 * which defined in arch/arm/mach-imx/pm-imx6q.c, this
135 /* let DDR out of self-refresh */
144 /* enable DDR auto power saving */
190 * put DDR explicitly into self-refresh and
191 * disable automatic power savings.
197 /* make the DDR explicitly enter self-refresh. */
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/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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/openbmc/linux/arch/x86/include/uapi/asm/
H A Damd_hsmp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
19 HSMP_GET_SOCKET_POWER, /* 04h average package power consumption */
20 HSMP_SET_SOCKET_POWER_LIMIT, /* 05h Set the socket power limit */
21 HSMP_GET_SOCKET_POWER_LIMIT, /* 06h Get current socket power limit */
22 HSMP_GET_SOCKET_POWER_LIMIT_MAX,/* 07h Get maximum socket power value */
29 HSMP_SET_AUTO_DF_PSTATE, /* 0Eh Enable DF P-State Performance Boost algorithm */
37 HSMP_GET_DIMM_TEMP_RANGE, /* 16h Get per-DIMM temperature range and refresh rate */
38 HSMP_GET_DIMM_POWER, /* 17h Get per-DIMM power consumption */
39 HSMP_GET_DIMM_THERMAL, /* 18h Get per-DIMM thermal sensors */
42 HSMP_GET_RAILS_SVI, /* 1Bh Get SVI-based Telemetry for all rails */
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/openbmc/linux/drivers/gpu/drm/bridge/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
26 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
50 ChromeOS EC ANX7688 is an ultra-low power
51 4K Ultra-HD (4096x2160p60) mobile HD transmitter
53 2.0 to DisplayPort 1.3 Ultra-HD. It is connected
60 Driver for display connectors with support for DDC and hot-plug
64 on ARM-based platforms. Saying Y here when this driver is not needed
74 Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
105 The module will be named "lontium-lt8912b".
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/openbmc/u-boot/board/ge/mx53ppd/
H A Dmx53ppd_video.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/iomux-mx53.h>
18 #include <asm/arch/imx-regs.h>
26 .name = "NV-SPWGRGB888",
27 .refresh = 60,
82 /* Set LDB_DI0 as clock source for IPU_DI0 */ in lcd_enable()
83 clrsetbits_le32(&mxc_ccm->cscmr2, in lcd_enable()
89 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3)); in lcd_enable()
92 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3)); in lcd_enable()
98 &iomux->gpr[2]); in lcd_enable()
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/openbmc/webui-vue/src/locales/
H A Den-US.json18 "refresh": "Refresh", string
95 "power": "Power", string
97 "refresh": "Refresh", string
102 "titleRefresh": "Refresh application data"
134 "power": "@:appPageTitle.power", string
139 "power": "Power", string
155 "powerRestorePolicy": "Power restore policy",
161 "serverPowerOperations": "Server power operations",
206 "label": "24-hour time",
251 …"successStartBmcDump": "The dump will take some time to complete. Refresh the application to see t…
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/openbmc/linux/arch/m68k/include/asm/
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
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H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-victgo.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
9 #include "imx6qdl-vicut1.dtsi"
15 gpio-keys {
16 compatible = "gpio-keys";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_gpiokeys>;
21 key-power {
22 label = "Power Button";
25 wakeup-source;
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/openbmc/linux/drivers/soc/ti/
H A Dpm33xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * AM33XX Power Management Routines
5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
17 #include <linux/nvmem-consumer.h>
24 #include <linux/rtc/rtc-omap.h>
28 #include <linux/ti-emif-sram.h>
31 #include <asm/proc-fns.h>
35 #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
36 (unsigned long)pm_sram->do_wfi)
104 pm_sram->do_wfi, in am33xx_push_sram_idle()
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/openbmc/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hwseq.c61 hws->ctx
63 hws->regs->reg
65 dc->ctx->logger
70 hws->shifts->field_name, hws->masks->field_name
75 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
79 if (plane_state->blend_tf) { in dcn30_set_blend_lut()
80 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) in dcn30_set_blend_lut()
81 blend_lut = &plane_state->blend_tf->pwl; in dcn30_set_blend_lut()
82 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { in dcn30_set_blend_lut()
84 plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
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/openbmc/u-boot/board/advantech/dms-ba16/
H A Ddms-ba16.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/mx6-pins.h>
14 #include <asm/mach-imx/mxc_i2c.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/video.h>
63 gd->ram_size = imx_ddr_size(); in dram_init()
199 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; in board_spi_cs_gpio()
236 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; in board_mmc_getcd()
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/openbmc/u-boot/board/aristainetos/
H A Daristainetos.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/mx6-pins.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/video.h>
62 #include "./aristainetos-v1.c"
64 #include "./aristainetos-v2.c"
105 gd->ram_size = imx_ddr_size(); in dram_init()
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/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
459 … //Only applicable to memory clock change, when set, using memory self refresh during clock tran…
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