arm/mach-at91/pm_suspend.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
16 .arch armv7-a
28  * Wait until master clock is ready (after switching master clock source)
91  * Set state for 2.5V low power regulator
92  * @ena: 0 - disable regulator
93  *	 1 - enable regulator
125  * Enable self-refresh
164 	/* Switch to self-refresh. */
170 	/* Wait for self-refresh enter. */
176 	/* Disable DX DLLs for non-backup modes. */
195 	/* Power down DDR PHY data receivers. */
200 	/* Power down ADDR/CMD IO. */
207 	/* Power down ODT. */
214  * Disable self-refresh
222 	/* Power up DDR PHY data receivers. */
227 	/* Power up the output of CK and CS pins. */
234 	/* Power up ODT. */
248 	/* Enable quasi-dynamic programming. */
252 	/* De-assert SDRAM initialization. */
257 	/* Quasi-dynamic programming done. */
266 	/* DLL soft-reset + DLL lock wait + ITM reset */
277 	/* Enable quasi-dynamic programming. */
296 	/* Trigger self-refresh exit. */
302 	/* Wait for self-refresh exit done. */
333  * Enable self-refresh
347 	/* Active SDRAM self-refresh mode */
360 	/* LPDDR1 --> force DDR2 mode during self-refresh */
370 	/* Active DDRC self-refresh mode */
391 	/* Active DDRC self-refresh mode */
405 	/* Active SDRAMC self-refresh mode */
419  * Disable self-refresh
438 	  * For exiting the self-refresh mode, do nothing,
439 	  * automatically exit the self-refresh mode.
484 	/* Set highest prescaler for power saving */
565  * the external crystal oscillator as a main clock source.
590 	/* Switch the main clock source to 12-MHz RC oscillator */
606 	/* Switch the master clock source to main clock */
636 	/* Switch the master clock source to slow clock */
643 	/* Switch main clock source to crystal oscillator */
652 	/* Switch the master clock source to main clock */
941 	 * Set master clock source to:
942 	 * - MAINCK if using ULP0 fast variant
943 	 * - slow clock, otherwise
957 	/* Enable low power mode for 2.5V regulator. */
972 	/* Disable low power mode for 2.5V regulator. */
993 	/* Switch the master clock source to slow clock. */
1026 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
1030 	stmfd	sp!, {r4 - r12, lr}
1051 	 * to RAM may be limited while in self-refresh.
1086 	/* Active the self-refresh mode */
1108 	/* Exit the self-refresh mode */
1112 	ldmfd	sp!, {r4 - r12, pc}
1161 	.word .-at91_pm_suspend_in_sram