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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Drealtek.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek switches for unmanaged switches
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - Linus Walleij <linus.walleij@linaro.org>
16 Realtek advertises these chips as fast/gigabit switches or unmanaged
18 MDIO or SPI.
20 The SMI "Simple Management Interface" is a two-wire protocol using
[all …]
/openbmc/linux/drivers/net/dsa/realtek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Realtek Ethernet switch family support"
10 Select to enable support for Realtek Ethernet switch chips.
19 tristate "Realtek MDIO interface driver"
26 through MDIO.
29 tristate "Realtek SMI interface driver"
39 tristate "Realtek RTL8365MB switch subdriver"
44 Select to enable support for Realtek RTL8365MB-VC and RTL8367S.
47 tristate "Realtek RTL8366RB switch subdriver"
52 Select to enable support for Realtek RTL8366RB.
H A Drealtek-smi.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek Simple Management Interface (SMI) driver
5 * The SMI protocol piggy-backs the MDIO MDC and MDIO signals levels
6 * but the protocol is not MDIO at all. Instead it is a Realtek
7 * pecularity that need to bit-bang the lines in a special way to
12 * RTL8366 - The original version, apparently
13 * RTL8369 - Similar enough to have the same datsheet as RTL8366
14 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
16 * RTL8366S - Is this "RTL8366 super"?
17 * RTL8367 - Has an OpenWRT driver as well
[all …]
H A Drealtek-mdio.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek MDIO interface driver
6 * RTL8366 - The original version, apparently
7 * RTL8369 - Similar enough to have the same datsheet as RTL8366
8 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
10 * RTL8366S - Is this "RTL8366 super"?
11 * RTL8367 - Has an OpenWRT driver as well
12 * RTL8368S - Seems to be an alternative name for RTL8366RB
13 * RTL8370 - Also uses SMI
19 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_NET_DSA_REALTEK_MDIO) += realtek-mdio.o
3 obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o
4 obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o
5 rtl8366-objs := rtl8366-core.o rtl8366rb.o
6 obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47094-asus-rt-ac88u.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "bcm47094-asus-rt-ac3100.dtsi"
11 compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
12 model = "ASUS RT-AC88U";
20 compatible = "realtek,rtl8365mb";
21 /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
22 mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
23 mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
24 reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Drealtek,rtl82xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL82xx PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
15 Bindings for Realtek RTL82xx PHYs
18 - $ref: ethernet-phy.yaml#
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/openbmc/u-boot/drivers/net/phy/
H A DKconfig3 bool "Bit-banged ethernet MII management channel support"
79 via MDIO commands. The firmware is loaded from a file, specified by
145 is supported through the 'mdio' command and any RGMII signal
172 bool "Realtek Ethernet PHYs support"
178 Configure the Realtek RTL8211E found on some Pine64+ models differently to
181 section of the RTL8211E datasheet, but come from Realtek by way of the
185 bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
188 Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
221 bool "Fixed-Link PHY"
224 Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
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/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
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H A Dgemini-dlink-dns-313.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
14 compatible = "dlink,dns-313", "cortina,gemini";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
[all …]
/openbmc/u-boot/drivers/net/
H A DKconfig11 This is currently implemented in net/eth-uclass.c
43 bool "Altera Triple-Speed Ethernet MAC support"
47 This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
48 Please find details on the "Triple-Speed Ethernet MegaCore Function
134 U-Boot.
152 in U-Boot to the RAW AF_PACKET API in Linux. This allows real
181 bool "Share the MDIO bus for FEC controller"
185 hex "MDIO base address for the FEC controller"
188 This specifies the MDIO registers base address. It is used when
189 two FEC controllers share MDIO bus.
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/openbmc/linux/drivers/net/dsa/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 tristate "DSA mock-up Ethernet switch chip support"
24 This enables support for a fake mock-up switch chip which
44 switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
45 MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
49 tristate "MediaTek MT7530 MDIO interface driver"
55 chips which are connected via MDIO, as well as multi-chip
65 This enables support for the built-in Ethernet switch found
69 accessible via MDIO.
90 source "drivers/net/dsa/realtek/Kconfig"
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm-sf2.o
3 bcm-sf2-objs := bcm_sf2.o bcm_sf2_cfp.o
4 obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o
6 obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdinfo.o
8 obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
9 obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
10 obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
11 obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
12 obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
[all …]
/openbmc/linux/drivers/net/phy/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
4 libphy-y := phy.o phy-c45.o phy-core.o phy_device.o \
6 mdio-bus-y += mdio_bus.o mdio_device.o
9 obj-y += mdio-boardinfo.o
13 # dependencies that does not make it possible to split mdio-bus objects into a
16 libphy-y += $(mdio-bus-y)
17 # the stubs are built-in whenever PHYLIB is built-in or module
18 obj-y += stubs.o
20 obj-$(CONFIG_MDIO_DEVICE) += mdio-bus.o
22 obj-$(CONFIG_MDIO_DEVRES) += mdio_devres.o
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 Adds support for a set of LED trigger events per-PHY. Link
39 logical-or of all the link speed ones.
55 tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
58 Adds the platform "fixed" MDIO Bus to cover the boards that use
59 PHYs that are not connected to the real MDIO bus.
61 Currently tested with mpc866ads and mpc8349e-mitx.
88 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
89 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
97 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
[all …]
H A Drealtek.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
4 * Driver for Realtek PHYs
76 MODULE_DESCRIPTION("Realtek PHY driver");
99 struct device *dev = &phydev->mdio.dev; in rtl821x_probe()
101 u32 phy_id = phydev->drv->phy_id; in rtl821x_probe()
106 return -ENOMEM; in rtl821x_probe()
108 priv->clk = devm_clk_get_optional_enabled(dev, NULL); in rtl821x_probe()
109 if (IS_ERR(priv->clk)) in rtl821x_probe()
110 return dev_err_probe(dev, PTR_ERR(priv->clk), in rtl821x_probe()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-debix-som-a-bmb-08.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mp-debix-som-a.dtsi"
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
22 stdout-path = &uart2;
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b-ec100.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
35 gpio-keys {
36 compatible = "gpio-keys-polled";
[all …]
H A Dmeson8m2-mxiii-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Oleg Ivanov <balbes-150@yandex.ru>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2";
26 stdout-path = "serial0:115200n8";
34 adc-keys {
35 compatible = "adc-keys";
36 io-channels = <&saradc 0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
15 model = "Hardkernel ODROID-C2";
23 stdout-path = "serial0:115200n8";
31 usb_otg_pwr: regulator-usb-pwrs {
32 compatible = "regulator-fixed";
34 regulator-name = "USB_OTG_PWR";
[all …]
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
20 stdout-path = "serial0:115200n8";
29 compatible = "gpio-leds";
32 label = "nanopi-k2:blue:stat";
34 default-state = "on";
35 panic-indicator;
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Drtl8723b_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
10 #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
81 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
82 #define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */
83 #define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */
87 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
190 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
216 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-wetek.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
19 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
30 led-power {
31 /* red in suspend or power-off */
35 default-state = "on";
36 panic-indicator;
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-ixdpg425.dts1 // SPDX-License-Identifier: ISC
5 * Ethernet set-up from OpenWrt.
15 /dts-v1/;
17 #include "intel-ixp42x.dtsi"
18 #include <dt-bindings/input/input.h>
23 #address-cells = <1>;
24 #size-cells = <1>;
34 stdout-path = "uart0:115200n8";
44 compatible = "intel,ixp4xx-flash", "cfi-flash";
45 bank-width = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3308-rock-pi-s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
24 stdout-path = "serial0:1500000n8";
28 compatible = "gpio-leds";
29 pinctrl-names = "default";
30 pinctrl-0 = <&green_led>, <&heartbeat_led>;
32 green-led {
34 default-state = "on";
38 linux,default-trigger = "default-on";
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