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12

/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Drenesas,wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/renesas,wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Watchdog Timer (WDT) Controller
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - items:
17 - enum:
18 - renesas,r7s72100-wdt # RZ/A1
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77990.dtsi1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a53", "arm,armv8";
25 power-domains = <&sysc 5>;
[all …]
H A Dr8a77995.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
18 /* External CAN clock - to be overridden by boards that provide it */
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <0>;
[all …]
H A Dr8a77970.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a77970-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
H A Dr8a77965.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a77965-sysc.h>
19 #address-cells = <2>;
20 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 compatible = "fixed-clock";
[all …]
H A Dr8a7796.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
[all …]
H A Dr8a7795.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
42 compatible = "fixed-clock";
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77970.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3M (R8A77970) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a77970-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
[all …]
H A Dr8a77995.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
[all …]
H A Dr8a77980.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
21 compatible = "fixed-clock";
[all …]
H A Dr8a77990.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
[all …]
H A Dr8a774c0.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
[all …]
H A Dr8a77965.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a77965-sysc.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
[all …]
H A Dr8a774b1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774b1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
H A Dr8a774a1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774a1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
H A Dr8a77961.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77961-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
[all …]
H A Dr8a77960.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
[all …]
H A Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
[all …]
H A Dr8a774e1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
H A Dr9a09g011.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a09g011-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
H A Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
[all …]
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
/openbmc/linux/drivers/soc/renesas/
H A Drcar-rst.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
11 #include <linux/soc/renesas/rcar-rst.h>
38 * Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
47 return -EINVAL; in rcar_rst_set_gen3_rproc_boot_addr()
76 /* V3U firmware doesn't enable WDT reset and there won't be updates anymore */
87 /* RZ/G1 is handled like R-Car Gen2 */
88 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
89 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
90 { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
[all …]
/openbmc/linux/drivers/watchdog/
H A Drenesas_wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog driver for Renesas WDT watchdog
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
33 * divider (12 bits). d is only a factor to fully utilize the WDT counter and
37 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
39 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
40 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
64 writel_relaxed(val, priv->base + reg); in rwdt_write()
71 rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); in rwdt_init_timeout()
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr7s9210.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
20 #clock-cells = <0>;
21 compatible = "fixed-clock";
23 clock-frequency = <0>;
27 #clock-cells = <0>;
[all …]

12