| /openbmc/linux/include/linux/ |
| H A D | hp_sdc.h | 2 * HP i8042 System Device Controller -- header
10 * 1. Redistributions of source code must retain the above copyright
31 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
34 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
104 #define HP_SDC_STATUS_PUP 0x70 /* Successful power-up self test */
134 #define HP_SDC_STR 0x7f /* i8042 self-test result */
146 #define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */
149 #define HP_SDC_CFG_KBD_OLD 0x03 /* keyboard code for non-HIL */
150 #define HP_SDC_CFG_KBD_NEW 0x07 /* keyboard code from HIL autoconfig */
151 #define HP_SDC_CFG_REV 0x40 /* Code revision bit */
[all …]
|
| /openbmc/u-boot/doc/ |
| H A D | README.ramboot-ppc85xx | 5 pre-mechanism is required to load the DDR with the bootloader binary.
6 - In case of SD and SPI boot this is done by BootROM code inside the chip
8 - In case of NAND boot FCM supports loading initial 4K code from NAND flash
15 1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then
18 - In very early stage of platform bringup where other boot options are not
20 - In case the support to program the flashes on the board is not available.
22 2. Load the RAM based bootloader onto DDR using already existing bootloader on
25 - While developing some new feature of u-boot, for example USB driver or
31 - Suppose a platform already has a propreitery bootloader which does not
32 support for example AMP boot. In this case also RAM boot loader can be
[all …]
|
| H A D | README.memory-test | 1 The most frequent cause of problems when porting U-Boot to new
8 U-Boot implements 3 different approaches to perform memory tests:
12 This function is supposed to be used in each and every U-Boot port
14 memory banks on this piece of hardware. The code is supposed to be
16 little known and generally underrated fact that this code will also
19 each and every port of U-Boot.
23 This is probably the best known memory test utility in U-Boot.
29 - It is terribly slow. Running "mtest" on the whole system RAM
33 - It is difficult to configure, and to use. And any errors here
36 purposes, like exception code, U-Boot code and data, stack,
[all …]
|
| H A D | README.arm-relocation | 3 At arch level: add linker flag -pie
10 (program-base-relative) and 2 (symbol-relative)
16 code to access these tables
25 detect the real dramsize, and store it in gd->ram_size. Bst detected
35 Board.c code is adapted from ppc code
41 -----------------------------------------------------------------------------
44 if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code
50 b) it copies the first page in nand to internal ram
51 (spl code)
52 c) end executes this code
[all …]
|
| /openbmc/qemu/migration/ |
| H A D | postcopy-ram.h | 2 * Postcopy migration for RAM
10 * See the COPYING file in the top-level directory.
16 #include "qapi/qapi-types-migration.h"
18 /* Return true if the host supports everything we need to do postcopy-ram */
23 * Make all of RAM sensitive to accesses to areas that haven't yet been written
29 * Initialise postcopy-ram, setting the RAM to a state where we can go into
31 * called from ram.c's similarly named ram_postcopy_incoming_init
41 * Userfault requires us to mark RAM as NOHUGEPAGE prior to discard
48 * Called at the start of each RAMBlock by the bitmap code.
53 * Called by the bitmap code for each chunk to discard.
[all …]
|
| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | emc.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch-tegra/ap.h>
10 #include <asm/arch-tegra/apb_misc.h>
94 ERR_NO_EMC_NODE = -10,
104 * Find EMC tables for the given ram code.
106 * The tegra EMC binding has two options, one using the ram code and one not.
107 * We detect which is in use by looking for the nvidia,use-ram-code property.
109 * otherwise we select the correct emc-tables subnode based on the 'ram_code'
113 * @param node EMC node (nvidia,tegra20-emc compatible string)
114 * @param ram_code RAM code to select (0-3, or -1 if unknown)
[all …]
|
| /openbmc/linux/Documentation/arch/arm/ |
| H A D | porting.rst | 5 Taken from list archive at http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2001-July/00406…
8 -------------------
14 phys = virt - PAGE_OFFSET + PHYS_OFFSET
18 --------------------
23 the time when you call the decompressor code. You normally call
25 to be located in RAM, it can be in flash or other read-only or
26 read-write addressable medium.
29 Start address of zero-initialised work area for the decompressor.
30 This must be pointing at RAM. The decompressor will zero initialise
43 Physical address to place the initial RAM disk. Only relevant if
[all …]
|
| H A D | tcm.rst | 2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
32 place you put it, it will mask any underlying RAM from the
33 CPU so it is usually wise not to overlap any physical RAM with
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
[all …]
|
| /openbmc/linux/drivers/net/ethernet/amd/ |
| H A D | mvme147.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Uses the generic 7990.c LANCE code.
30 /* We have 32K of RAM for the init block and buffers. This places
37 #include "7990.h" /* use generic LANCE code */
42 unsigned long ram; member
47 * plus board-specific init, open and close actions.
48 * Oh, and we need to tell the generic code how to read and write LANCE registers...
70 /* Initialise the one and only on-board 7990 */
83 return ERR_PTR(-ENODEV); in mvme147lance_probe()
88 return ERR_PTR(-ENOMEM); in mvme147lance_probe()
[all …]
|
| /openbmc/qemu/docs/devel/migration/ |
| H A D | best-practices.rst | 8 The migration stream can be analyzed thanks to ``scripts/analyze-migration.py``.
12 .. code-block:: shell
14 $ qemu-system-x86_64 -display none -monitor stdio
17 $ ./scripts/analyze-migration.py -f mig
19 "ram (3)": {
21 "pc.ram": "0x0000000008000000",
24 See also ``analyze-migration.py -h`` help for more options.
29 Migration migrates the copies of RAM and ROM, and thus when running
34 - Changes in firmware size can cause changes in the required RAMBlock size
39 - Care should be taken with device emulation code so that newer
[all …]
|
| /openbmc/u-boot/lib/lzma/ |
| H A D | lzma.txt | 2 -------------
8 in 7-Zip compression program (www.7-zip.org). LZMA provides high
19 -------
23 Some code in LZMA SDK is based on public domain code from another developers:
25 2) SHA-256: Wei Dai (Crypto++ library)
29 -----------------
33 - ANSI-C/C++/C#/Java source code for LZMA compressing and decompressing
34 - Compiled file->file LZMA compressing/decompressing program for Windows system
38 ------------------
39 To compile C++ version of file->file LZMA encoding, go to directory
[all …]
|
| /openbmc/linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_nvm.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
10 * i40e_init_nvm - Initialize NVM function pointers
17 * We are accessing FLASH always thru the Shadow RAM.
21 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_init_nvm()
33 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; in i40e_init_nvm()
39 nvm->timeout = I40E_MAX_NVM_TIMEOUT; in i40e_init_nvm()
40 nvm->blank_nvm_mode = false; in i40e_init_nvm()
42 nvm->blank_nvm_mode = true; in i40e_init_nvm()
43 ret_code = -EIO; in i40e_init_nvm()
[all …]
|
| /openbmc/qemu/tests/functional/ |
| H A D | test_mem_addr_space.py | 11 # SPDX-License-Identifier: GPL-2.0-or-later
23 # first, lets test some 32-bit processors.
24 # for all 32-bit cases, pci64_hole_size is 0.
36 Note that 64-bit pci hole size is 0 in this case. If maxmem is set to
37 59.6G, QEMU should fail to start with a message "phy-bits are too low".
41 self.vm.add_args('-S', '-machine', 'q35', '-m',
43 '-cpu', 'pentium,pse36=on', '-display', 'none',
44 '-object', 'memory-backend-ram,id=mem1,size=1G',
45 '-device', 'pc-dimm,id=vm0,memdev=mem1')
49 self.assertEqual(self.vm.exitcode(), 1, "QEMU exit code should be 1")
[all …]
|
| /openbmc/u-boot/arch/arm/lib/ |
| H A D | crt0_64.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * crt0 - C-runtime startup Code for AArch64 U-Boot
13 #include <asm-offsets.h>
18 * This file handles the target-independent stages of the U-Boot
19 * start-up where a C runtime environment is needed. Its entry point
27 * available RAM (SRAM, locked cache...). In this context, VARIABLE
33 * execution from system RAM (DRAM, DDR...) As system RAM may not
40 * ones allocated by board_init_f() in system RAM, but BSS and
41 * initialized non-const data are still not available.
43 * 4a.For U-Boot proper (not SPL), call relocate_code(). This function
[all …]
|
| /openbmc/docs/architecture/code-update/ |
| H A D | code-update-deprecated.md | 1 # OpenBMC Code Update
5 - The REST APIs described below are deprecated. Please follow
6 [code-update.md](code-update.md) for the new APIs to do code update.
7 - The rest part of this document is still valid.
9 The host code update can be found here:
10 [host-code-update.md](host-code-update.md)
13 `tmp/deploy/images/<platform>/`. The `image-*` symlinks correspond to components
16 - `image-bmc` → `obmc-phosphor-image-<platform>-<timestamp>.static.mtd`
20 - `image-kernel` → `fitImage-obmc-phosphor-initramfs-<platform>.bin`
25 - `image-rofs` → `obmc-phosphor-image-<platform>.squashfs-xz`
[all …]
|
| /openbmc/u-boot/board/freescale/m547xevb/ |
| H A D | README | 4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
13 - board/freescale/m547xevb/mii.c MII init
14 - board/freescale/m547xevb/Makefile Makefile
15 - board/freescale/m547xevb/config.mk config make
16 - board/freescale/m547xevb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
20 - arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
[all …]
|
| /openbmc/u-boot/arch/x86/cpu/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * U-Boot - x86 Startup Code
5 * (C) Copyright 2008-2011
16 #include <asm/processor-flags.h>
17 #include <generated/generic-asm-offsets.h>
18 #include <generated/asm-offsets.h>
28 * This is the fail-safe 32-bit bootstrap entry point.
30 * This code is used when booting from another boot loader like
37 /* Turn off cache (this might require a 486-class CPU) */
43 /* Tell 32-bit code it is being entered from an in-RAM copy */
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra20-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
23 const: nvidia,tegra20-emc
[all …]
|
| /openbmc/linux/arch/arm/kernel/ |
| H A D | tcm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2009 ST-Ericsson AB
41 .name = "DTCM RAM",
48 .name = "ITCM RAM",
114 const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128, in setup_tcm_bank()
115 256, 512, 1024, -1, -1, -1, -1 }; in setup_tcm_bank()
141 return -EINVAL; in setup_tcm_bank()
145 return -EINVAL; in setup_tcm_bank()
183 * When we are running in the non-secure world and the secure world
200 * In this particular case (MRC with ARM condition code ALways) the
[all …]
|
| /openbmc/u-boot/arch/riscv/cpu/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
12 #include <asm-offsets.h>
17 #include <generated/asm-offsets.h>
53 * Set stackpointer in internal/ex RAM to call board_init_f
56 li t0, -16
77 mv a0, zero /* a0 <-- boot_flags = 0 */
84 * This "function" does not return, instead it continues in RAM
85 * after relocating the monitor code.
100 sub t6, s4, t0 /* t6 <- relocation offset */
[all …]
|
| /openbmc/u-boot/arch/m68k/cpu/mcf523x/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
7 #include <asm-offsets.h>
18 moveml %d0-%d7/%a0-%a6,%sp@;
21 moveml %sp@,%d0-%d7/%a0-%a6; \
29 * These vectors are to catch any un-intended traps.
46 /* TRAP #0 - #15 */
109 /* initialize general use internal ram */
119 /* setup stack initially on top of internal static ram */
126 move.l %sp, -(%sp)
[all …]
|
| /openbmc/u-boot/arch/m68k/cpu/mcf547x_8x/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
7 #include <asm-offsets.h>
18 moveml %d0-%d7/%a0-%a6,%sp@;
21 moveml %sp@,%d0-%d7/%a0-%a6; \
29 * These vectors are to catch any un-intended traps.
46 /* TRAP #0 - #15 */
116 /* initialize general use internal ram */
126 /* setup stack initially on top of internal static ram */
133 move.l %sp, -(%sp)
[all …]
|
| /openbmc/u-boot/include/ |
| H A D | fsl_qe.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
6 * based on source code of Shlomi Gridish
21 #define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
74 /* QE CECR Sub Block Code - sub block code of QE command.
108 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
219 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
220 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
221 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
223 /* I-RAM */
[all …]
|
| /openbmc/u-boot/arch/m68k/cpu/mcf530x/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
7 #include <asm-offsets.h>
19 moveml %d0-%d7/%a0-%a6,%sp@
23 moveml %sp@,%d0-%d7/%a0-%a6;
28 /* If we come from a pre-loader we don't need an initial exception
37 * These vectors are to catch any un-intended traps.
44 .long _start - CONFIG_SYS_TEXT_BASE
110 * if we come from a pre-loader we have no exception table and
118 /* initialize general use internal ram */
[all …]
|
| /openbmc/u-boot/arch/m68k/cpu/mcf532x/ |
| H A D | start.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
6 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 #include <asm-offsets.h>
21 moveml %d0-%d7/%a0-%a6,%sp@;
24 moveml %sp@,%d0-%d7/%a0-%a6; \
34 * These vectors are to catch any un-intended traps.
51 /* TRAP #0 - #15 */
124 /* initialize general use internal ram */
[all …]
|