1ae06c70bSJeff Kirsher // SPDX-License-Identifier: GPL-2.0
251dce24bSJeff Kirsher /* Copyright(c) 2013 - 2018 Intel Corporation. */
356a62fc8SJesse Brandeburg
4*e383353bSJesse Brandeburg #include <linux/bitfield.h>
5e77220eeSIvan Vecera #include <linux/delay.h>
6e77220eeSIvan Vecera #include "i40e_alloc.h"
756a62fc8SJesse Brandeburg #include "i40e_prototype.h"
856a62fc8SJesse Brandeburg
956a62fc8SJesse Brandeburg /**
10262de08fSJesse Brandeburg * i40e_init_nvm - Initialize NVM function pointers
113e26186dSShannon Nelson * @hw: pointer to the HW structure
1256a62fc8SJesse Brandeburg *
133e26186dSShannon Nelson * Setup the function pointers and the NVM info structure. Should be called
1456a62fc8SJesse Brandeburg * once per NVM initialization, e.g. inside the i40e_init_shared_code().
1556a62fc8SJesse Brandeburg * Please notice that the NVM term is used here (& in all methods covered
1656a62fc8SJesse Brandeburg * in this file) as an equivalent of the FLASH part mapped into the SR.
1756a62fc8SJesse Brandeburg * We are accessing FLASH always thru the Shadow RAM.
1856a62fc8SJesse Brandeburg **/
i40e_init_nvm(struct i40e_hw * hw)195180ff13SJan Sokolowski int i40e_init_nvm(struct i40e_hw *hw)
2056a62fc8SJesse Brandeburg {
2156a62fc8SJesse Brandeburg struct i40e_nvm_info *nvm = &hw->nvm;
225180ff13SJan Sokolowski int ret_code = 0;
2356a62fc8SJesse Brandeburg u32 fla, gens;
2456a62fc8SJesse Brandeburg u8 sr_size;
2556a62fc8SJesse Brandeburg
2656a62fc8SJesse Brandeburg /* The SR size is stored regardless of the nvm programming mode
2756a62fc8SJesse Brandeburg * as the blank mode may be used in the factory line.
2856a62fc8SJesse Brandeburg */
2956a62fc8SJesse Brandeburg gens = rd32(hw, I40E_GLNVM_GENS);
3056a62fc8SJesse Brandeburg sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
3156a62fc8SJesse Brandeburg I40E_GLNVM_GENS_SR_SIZE_SHIFT);
323e26186dSShannon Nelson /* Switching to words (sr_size contains power of 2KB) */
3341a1d04bSJesse Brandeburg nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
3456a62fc8SJesse Brandeburg
353e26186dSShannon Nelson /* Check if we are in the normal or blank NVM programming mode */
3656a62fc8SJesse Brandeburg fla = rd32(hw, I40E_GLNVM_FLA);
373e26186dSShannon Nelson if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
383e26186dSShannon Nelson /* Max NVM timeout */
3956a62fc8SJesse Brandeburg nvm->timeout = I40E_MAX_NVM_TIMEOUT;
4056a62fc8SJesse Brandeburg nvm->blank_nvm_mode = false;
413e26186dSShannon Nelson } else { /* Blank programming mode */
4256a62fc8SJesse Brandeburg nvm->blank_nvm_mode = true;
43230f3d53SJan Sokolowski ret_code = -EIO;
4474d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
4556a62fc8SJesse Brandeburg }
4656a62fc8SJesse Brandeburg
4756a62fc8SJesse Brandeburg return ret_code;
4856a62fc8SJesse Brandeburg }
4956a62fc8SJesse Brandeburg
5056a62fc8SJesse Brandeburg /**
513e26186dSShannon Nelson * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
523e26186dSShannon Nelson * @hw: pointer to the HW structure
533e26186dSShannon Nelson * @access: NVM access type (read or write)
5456a62fc8SJesse Brandeburg *
5556a62fc8SJesse Brandeburg * This function will request NVM ownership for reading
5656a62fc8SJesse Brandeburg * via the proper Admin Command.
5756a62fc8SJesse Brandeburg **/
i40e_acquire_nvm(struct i40e_hw * hw,enum i40e_aq_resource_access_type access)585180ff13SJan Sokolowski int i40e_acquire_nvm(struct i40e_hw *hw,
5956a62fc8SJesse Brandeburg enum i40e_aq_resource_access_type access)
6056a62fc8SJesse Brandeburg {
6156a62fc8SJesse Brandeburg u64 gtime, timeout;
62c509c1deSShannon Nelson u64 time_left = 0;
635180ff13SJan Sokolowski int ret_code = 0;
6456a62fc8SJesse Brandeburg
6556a62fc8SJesse Brandeburg if (hw->nvm.blank_nvm_mode)
6656a62fc8SJesse Brandeburg goto i40e_i40e_acquire_nvm_exit;
6756a62fc8SJesse Brandeburg
6856a62fc8SJesse Brandeburg ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
69c509c1deSShannon Nelson 0, &time_left, NULL);
703e26186dSShannon Nelson /* Reading the Global Device Timer */
7156a62fc8SJesse Brandeburg gtime = rd32(hw, I40E_GLVFGEN_TIMER);
7256a62fc8SJesse Brandeburg
733e26186dSShannon Nelson /* Store the timeout */
74c509c1deSShannon Nelson hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
7556a62fc8SJesse Brandeburg
76a3f0b381SShannon Nelson if (ret_code)
77a3f0b381SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
78a3f0b381SShannon Nelson "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
79a3f0b381SShannon Nelson access, time_left, ret_code, hw->aq.asq_last_status);
80a3f0b381SShannon Nelson
81a3f0b381SShannon Nelson if (ret_code && time_left) {
823e26186dSShannon Nelson /* Poll until the current NVM owner timeouts */
83c509c1deSShannon Nelson timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
84a3f0b381SShannon Nelson while ((gtime < timeout) && time_left) {
8556a62fc8SJesse Brandeburg usleep_range(10000, 20000);
86c509c1deSShannon Nelson gtime = rd32(hw, I40E_GLVFGEN_TIMER);
8756a62fc8SJesse Brandeburg ret_code = i40e_aq_request_resource(hw,
8856a62fc8SJesse Brandeburg I40E_NVM_RESOURCE_ID,
89c509c1deSShannon Nelson access, 0, &time_left,
9056a62fc8SJesse Brandeburg NULL);
9156a62fc8SJesse Brandeburg if (!ret_code) {
9256a62fc8SJesse Brandeburg hw->nvm.hw_semaphore_timeout =
93c509c1deSShannon Nelson I40E_MS_TO_GTIME(time_left) + gtime;
9456a62fc8SJesse Brandeburg break;
9556a62fc8SJesse Brandeburg }
9656a62fc8SJesse Brandeburg }
9756a62fc8SJesse Brandeburg if (ret_code) {
9856a62fc8SJesse Brandeburg hw->nvm.hw_semaphore_timeout = 0;
9974d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
100a3f0b381SShannon Nelson "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
101a3f0b381SShannon Nelson time_left, ret_code, hw->aq.asq_last_status);
10256a62fc8SJesse Brandeburg }
10356a62fc8SJesse Brandeburg }
10456a62fc8SJesse Brandeburg
10556a62fc8SJesse Brandeburg i40e_i40e_acquire_nvm_exit:
10656a62fc8SJesse Brandeburg return ret_code;
10756a62fc8SJesse Brandeburg }
10856a62fc8SJesse Brandeburg
10956a62fc8SJesse Brandeburg /**
1103e26186dSShannon Nelson * i40e_release_nvm - Generic request for releasing the NVM ownership
1113e26186dSShannon Nelson * @hw: pointer to the HW structure
11256a62fc8SJesse Brandeburg *
11356a62fc8SJesse Brandeburg * This function will release NVM resource via the proper Admin Command.
11456a62fc8SJesse Brandeburg **/
i40e_release_nvm(struct i40e_hw * hw)11556a62fc8SJesse Brandeburg void i40e_release_nvm(struct i40e_hw *hw)
11656a62fc8SJesse Brandeburg {
117981e25c3SPaul M Stillwell Jr u32 total_delay = 0;
118230f3d53SJan Sokolowski int ret_code = 0;
119981e25c3SPaul M Stillwell Jr
120981e25c3SPaul M Stillwell Jr if (hw->nvm.blank_nvm_mode)
121981e25c3SPaul M Stillwell Jr return;
122981e25c3SPaul M Stillwell Jr
123981e25c3SPaul M Stillwell Jr ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
124981e25c3SPaul M Stillwell Jr
125981e25c3SPaul M Stillwell Jr /* there are some rare cases when trying to release the resource
126981e25c3SPaul M Stillwell Jr * results in an admin Q timeout, so handle them correctly
127981e25c3SPaul M Stillwell Jr */
128230f3d53SJan Sokolowski while ((ret_code == -EIO) &&
129981e25c3SPaul M Stillwell Jr (total_delay < hw->aq.asq_cmd_timeout)) {
130981e25c3SPaul M Stillwell Jr usleep_range(1000, 2000);
131981e25c3SPaul M Stillwell Jr ret_code = i40e_aq_release_resource(hw,
132981e25c3SPaul M Stillwell Jr I40E_NVM_RESOURCE_ID,
133981e25c3SPaul M Stillwell Jr 0, NULL);
134981e25c3SPaul M Stillwell Jr total_delay++;
135981e25c3SPaul M Stillwell Jr }
13656a62fc8SJesse Brandeburg }
13756a62fc8SJesse Brandeburg
13856a62fc8SJesse Brandeburg /**
1393e26186dSShannon Nelson * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
1403e26186dSShannon Nelson * @hw: pointer to the HW structure
14156a62fc8SJesse Brandeburg *
14256a62fc8SJesse Brandeburg * Polls the SRCTL Shadow RAM register done bit.
14356a62fc8SJesse Brandeburg **/
i40e_poll_sr_srctl_done_bit(struct i40e_hw * hw)1445180ff13SJan Sokolowski static int i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
14556a62fc8SJesse Brandeburg {
146230f3d53SJan Sokolowski int ret_code = -EIO;
14756a62fc8SJesse Brandeburg u32 srctl, wait_cnt;
14856a62fc8SJesse Brandeburg
1493e26186dSShannon Nelson /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
15056a62fc8SJesse Brandeburg for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
15156a62fc8SJesse Brandeburg srctl = rd32(hw, I40E_GLNVM_SRCTL);
15256a62fc8SJesse Brandeburg if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
15356a62fc8SJesse Brandeburg ret_code = 0;
15456a62fc8SJesse Brandeburg break;
15556a62fc8SJesse Brandeburg }
15656a62fc8SJesse Brandeburg udelay(5);
15756a62fc8SJesse Brandeburg }
158230f3d53SJan Sokolowski if (ret_code == -EIO)
15974d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
16056a62fc8SJesse Brandeburg return ret_code;
16156a62fc8SJesse Brandeburg }
16256a62fc8SJesse Brandeburg
16356a62fc8SJesse Brandeburg /**
164d1bbe0eaSKamil Krawczyk * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
1653e26186dSShannon Nelson * @hw: pointer to the HW structure
1663e26186dSShannon Nelson * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
1673e26186dSShannon Nelson * @data: word read from the Shadow RAM
16856a62fc8SJesse Brandeburg *
1693e26186dSShannon Nelson * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
17056a62fc8SJesse Brandeburg **/
i40e_read_nvm_word_srctl(struct i40e_hw * hw,u16 offset,u16 * data)1715180ff13SJan Sokolowski static int i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
17256a62fc8SJesse Brandeburg u16 *data)
17356a62fc8SJesse Brandeburg {
174230f3d53SJan Sokolowski int ret_code = -EIO;
17556a62fc8SJesse Brandeburg u32 sr_reg;
17656a62fc8SJesse Brandeburg
17756a62fc8SJesse Brandeburg if (offset >= hw->nvm.sr_size) {
17874d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
17974d0d0edSShannon Nelson "NVM read error: offset %d beyond Shadow RAM limit %d\n",
18074d0d0edSShannon Nelson offset, hw->nvm.sr_size);
181230f3d53SJan Sokolowski ret_code = -EINVAL;
18256a62fc8SJesse Brandeburg goto read_nvm_exit;
18356a62fc8SJesse Brandeburg }
18456a62fc8SJesse Brandeburg
1853e26186dSShannon Nelson /* Poll the done bit first */
18656a62fc8SJesse Brandeburg ret_code = i40e_poll_sr_srctl_done_bit(hw);
18756a62fc8SJesse Brandeburg if (!ret_code) {
1883e26186dSShannon Nelson /* Write the address and start reading */
18941a1d04bSJesse Brandeburg sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
19041a1d04bSJesse Brandeburg BIT(I40E_GLNVM_SRCTL_START_SHIFT);
19156a62fc8SJesse Brandeburg wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
19256a62fc8SJesse Brandeburg
1933e26186dSShannon Nelson /* Poll I40E_GLNVM_SRCTL until the done bit is set */
19456a62fc8SJesse Brandeburg ret_code = i40e_poll_sr_srctl_done_bit(hw);
19556a62fc8SJesse Brandeburg if (!ret_code) {
19656a62fc8SJesse Brandeburg sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
19756a62fc8SJesse Brandeburg *data = (u16)((sr_reg &
19856a62fc8SJesse Brandeburg I40E_GLNVM_SRDATA_RDDATA_MASK)
19956a62fc8SJesse Brandeburg >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
20056a62fc8SJesse Brandeburg }
20156a62fc8SJesse Brandeburg }
20256a62fc8SJesse Brandeburg if (ret_code)
20374d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
20474d0d0edSShannon Nelson "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
20556a62fc8SJesse Brandeburg offset);
20656a62fc8SJesse Brandeburg
20756a62fc8SJesse Brandeburg read_nvm_exit:
20856a62fc8SJesse Brandeburg return ret_code;
20956a62fc8SJesse Brandeburg }
21056a62fc8SJesse Brandeburg
21156a62fc8SJesse Brandeburg /**
2127073f46eSShannon Nelson * i40e_read_nvm_aq - Read Shadow RAM.
2137073f46eSShannon Nelson * @hw: pointer to the HW structure.
2147073f46eSShannon Nelson * @module_pointer: module pointer location in words from the NVM beginning
2157073f46eSShannon Nelson * @offset: offset in words from module start
2162f2beb88SAndrii Staikov * @words: number of words to read
2172f2beb88SAndrii Staikov * @data: buffer with words to read to the Shadow RAM
2187073f46eSShannon Nelson * @last_command: tells the AdminQ that this is the last command
2197073f46eSShannon Nelson *
2202f2beb88SAndrii Staikov * Reads a 16 bit words buffer to the Shadow RAM using the admin command.
2217073f46eSShannon Nelson **/
i40e_read_nvm_aq(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 words,void * data,bool last_command)2225180ff13SJan Sokolowski static int i40e_read_nvm_aq(struct i40e_hw *hw,
223e3a5d6e6SPawel Jablonski u8 module_pointer, u32 offset,
224e3a5d6e6SPawel Jablonski u16 words, void *data,
2257073f46eSShannon Nelson bool last_command)
2267073f46eSShannon Nelson {
2277073f46eSShannon Nelson struct i40e_asq_cmd_details cmd_details;
228230f3d53SJan Sokolowski int ret_code = -EIO;
2297073f46eSShannon Nelson
2307073f46eSShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details));
2313c8f3e96SJacob Keller cmd_details.wb_desc = &hw->nvm_wb_desc;
2327073f46eSShannon Nelson
2337073f46eSShannon Nelson /* Here we are checking the SR limit only for the flat memory model.
2347073f46eSShannon Nelson * We cannot do it for the module-based model, as we did not acquire
2357073f46eSShannon Nelson * the NVM resource yet (we cannot get the module pointer value).
2367073f46eSShannon Nelson * Firmware will check the module-based model.
2377073f46eSShannon Nelson */
2387073f46eSShannon Nelson if ((offset + words) > hw->nvm.sr_size)
2397073f46eSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
2402f2beb88SAndrii Staikov "NVM read error: offset %d beyond Shadow RAM limit %d\n",
2417073f46eSShannon Nelson (offset + words), hw->nvm.sr_size);
2427073f46eSShannon Nelson else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
2432f2beb88SAndrii Staikov /* We can read only up to 4KB (one sector), in one AQ write */
2447073f46eSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
2452f2beb88SAndrii Staikov "NVM read fail error: tried to read %d words, limit is %d.\n",
2467073f46eSShannon Nelson words, I40E_SR_SECTOR_SIZE_IN_WORDS);
2477073f46eSShannon Nelson else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
2487073f46eSShannon Nelson != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
2492f2beb88SAndrii Staikov /* A single read cannot spread over two sectors */
2507073f46eSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
2512f2beb88SAndrii Staikov "NVM read error: cannot spread over two sectors in a single read offset=%d words=%d\n",
2527073f46eSShannon Nelson offset, words);
2537073f46eSShannon Nelson else
2547073f46eSShannon Nelson ret_code = i40e_aq_read_nvm(hw, module_pointer,
2557073f46eSShannon Nelson 2 * offset, /*bytes*/
2567073f46eSShannon Nelson 2 * words, /*bytes*/
2577073f46eSShannon Nelson data, last_command, &cmd_details);
2587073f46eSShannon Nelson
2597073f46eSShannon Nelson return ret_code;
2607073f46eSShannon Nelson }
2617073f46eSShannon Nelson
2627073f46eSShannon Nelson /**
2637073f46eSShannon Nelson * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
2647073f46eSShannon Nelson * @hw: pointer to the HW structure
2657073f46eSShannon Nelson * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
2667073f46eSShannon Nelson * @data: word read from the Shadow RAM
2677073f46eSShannon Nelson *
26809f79fd4SAnjali Singhai Jain * Reads one 16 bit word from the Shadow RAM using the AdminQ
2697073f46eSShannon Nelson **/
i40e_read_nvm_word_aq(struct i40e_hw * hw,u16 offset,u16 * data)2705180ff13SJan Sokolowski static int i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
2717073f46eSShannon Nelson u16 *data)
2727073f46eSShannon Nelson {
273230f3d53SJan Sokolowski int ret_code = -EIO;
2747073f46eSShannon Nelson
2757073f46eSShannon Nelson ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
2767073f46eSShannon Nelson *data = le16_to_cpu(*(__le16 *)data);
2777073f46eSShannon Nelson
2787073f46eSShannon Nelson return ret_code;
2797073f46eSShannon Nelson }
2807073f46eSShannon Nelson
2817073f46eSShannon Nelson /**
282e836e321SStefano Brivio * __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking
283d1bbe0eaSKamil Krawczyk * @hw: pointer to the HW structure
284d1bbe0eaSKamil Krawczyk * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
285d1bbe0eaSKamil Krawczyk * @data: word read from the Shadow RAM
286d1bbe0eaSKamil Krawczyk *
28709f79fd4SAnjali Singhai Jain * Reads one 16 bit word from the Shadow RAM.
28809f79fd4SAnjali Singhai Jain *
28909f79fd4SAnjali Singhai Jain * Do not use this function except in cases where the nvm lock is already
29009f79fd4SAnjali Singhai Jain * taken via i40e_acquire_nvm().
29109f79fd4SAnjali Singhai Jain **/
__i40e_read_nvm_word(struct i40e_hw * hw,u16 offset,u16 * data)2925180ff13SJan Sokolowski static int __i40e_read_nvm_word(struct i40e_hw *hw,
29309f79fd4SAnjali Singhai Jain u16 offset, u16 *data)
29409f79fd4SAnjali Singhai Jain {
29509f79fd4SAnjali Singhai Jain if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
2962c4d36b7SStefano Brivio return i40e_read_nvm_word_aq(hw, offset, data);
2972c4d36b7SStefano Brivio
2982c4d36b7SStefano Brivio return i40e_read_nvm_word_srctl(hw, offset, data);
29909f79fd4SAnjali Singhai Jain }
30009f79fd4SAnjali Singhai Jain
30109f79fd4SAnjali Singhai Jain /**
30209f79fd4SAnjali Singhai Jain * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary
30309f79fd4SAnjali Singhai Jain * @hw: pointer to the HW structure
30409f79fd4SAnjali Singhai Jain * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
30509f79fd4SAnjali Singhai Jain * @data: word read from the Shadow RAM
30609f79fd4SAnjali Singhai Jain *
30709f79fd4SAnjali Singhai Jain * Reads one 16 bit word from the Shadow RAM.
308d1bbe0eaSKamil Krawczyk **/
i40e_read_nvm_word(struct i40e_hw * hw,u16 offset,u16 * data)3095180ff13SJan Sokolowski int i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
310d1bbe0eaSKamil Krawczyk u16 *data)
311d1bbe0eaSKamil Krawczyk {
3125180ff13SJan Sokolowski int ret_code = 0;
31307f89be8SAnjali Singhai
3143d72aebfSJacob Keller if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
31507f89be8SAnjali Singhai ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
31609f79fd4SAnjali Singhai Jain if (ret_code)
31709f79fd4SAnjali Singhai Jain return ret_code;
31809f79fd4SAnjali Singhai Jain
31909f79fd4SAnjali Singhai Jain ret_code = __i40e_read_nvm_word(hw, offset, data);
32009f79fd4SAnjali Singhai Jain
3213d72aebfSJacob Keller if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)
32296a39aedSAaron Salter i40e_release_nvm(hw);
32309f79fd4SAnjali Singhai Jain
32407f89be8SAnjali Singhai return ret_code;
325d1bbe0eaSKamil Krawczyk }
326d1bbe0eaSKamil Krawczyk
327d1bbe0eaSKamil Krawczyk /**
32865c275e4SSylwia Wnuczko * i40e_read_nvm_module_data - Reads NVM Buffer to specified memory location
329ff924657SSylwia Wnuczko * @hw: Pointer to the HW structure
33065c275e4SSylwia Wnuczko * @module_ptr: Pointer to module in words with respect to NVM beginning
331ff924657SSylwia Wnuczko * @module_offset: Offset in words from module start
332ff924657SSylwia Wnuczko * @data_offset: Offset in words from reading data area start
33365c275e4SSylwia Wnuczko * @words_data_size: Words to read from NVM
33465c275e4SSylwia Wnuczko * @data_ptr: Pointer to memory location where resulting buffer will be stored
33565c275e4SSylwia Wnuczko **/
i40e_read_nvm_module_data(struct i40e_hw * hw,u8 module_ptr,u16 module_offset,u16 data_offset,u16 words_data_size,u16 * data_ptr)3365180ff13SJan Sokolowski int i40e_read_nvm_module_data(struct i40e_hw *hw,
337ff924657SSylwia Wnuczko u8 module_ptr,
338ff924657SSylwia Wnuczko u16 module_offset,
339ff924657SSylwia Wnuczko u16 data_offset,
34065c275e4SSylwia Wnuczko u16 words_data_size,
34165c275e4SSylwia Wnuczko u16 *data_ptr)
34265c275e4SSylwia Wnuczko {
343ff924657SSylwia Wnuczko u16 specific_ptr = 0;
34465c275e4SSylwia Wnuczko u16 ptr_value = 0;
345ff924657SSylwia Wnuczko u32 offset = 0;
3465180ff13SJan Sokolowski int status;
34765c275e4SSylwia Wnuczko
34865c275e4SSylwia Wnuczko if (module_ptr != 0) {
34965c275e4SSylwia Wnuczko status = i40e_read_nvm_word(hw, module_ptr, &ptr_value);
35065c275e4SSylwia Wnuczko if (status) {
35165c275e4SSylwia Wnuczko i40e_debug(hw, I40E_DEBUG_ALL,
35265c275e4SSylwia Wnuczko "Reading nvm word failed.Error code: %d.\n",
35365c275e4SSylwia Wnuczko status);
354230f3d53SJan Sokolowski return -EIO;
35565c275e4SSylwia Wnuczko }
35665c275e4SSylwia Wnuczko }
35765c275e4SSylwia Wnuczko #define I40E_NVM_INVALID_PTR_VAL 0x7FFF
35865c275e4SSylwia Wnuczko #define I40E_NVM_INVALID_VAL 0xFFFF
35965c275e4SSylwia Wnuczko
36065c275e4SSylwia Wnuczko /* Pointer not initialized */
36165c275e4SSylwia Wnuczko if (ptr_value == I40E_NVM_INVALID_PTR_VAL ||
362ff924657SSylwia Wnuczko ptr_value == I40E_NVM_INVALID_VAL) {
363ff924657SSylwia Wnuczko i40e_debug(hw, I40E_DEBUG_ALL, "Pointer not initialized.\n");
364230f3d53SJan Sokolowski return -EINVAL;
365ff924657SSylwia Wnuczko }
36665c275e4SSylwia Wnuczko
36765c275e4SSylwia Wnuczko /* Check whether the module is in SR mapped area or outside */
36865c275e4SSylwia Wnuczko if (ptr_value & I40E_PTR_TYPE) {
36965c275e4SSylwia Wnuczko /* Pointer points outside of the Shared RAM mapped area */
370ff924657SSylwia Wnuczko i40e_debug(hw, I40E_DEBUG_ALL,
371ff924657SSylwia Wnuczko "Reading nvm data failed. Pointer points outside of the Shared RAM mapped area.\n");
37265c275e4SSylwia Wnuczko
373230f3d53SJan Sokolowski return -EINVAL;
374ff924657SSylwia Wnuczko } else {
375ff924657SSylwia Wnuczko /* Read from the Shadow RAM */
376ff924657SSylwia Wnuczko
377ff924657SSylwia Wnuczko status = i40e_read_nvm_word(hw, ptr_value + module_offset,
378ff924657SSylwia Wnuczko &specific_ptr);
37965c275e4SSylwia Wnuczko if (status) {
38065c275e4SSylwia Wnuczko i40e_debug(hw, I40E_DEBUG_ALL,
381ff924657SSylwia Wnuczko "Reading nvm word failed.Error code: %d.\n",
38265c275e4SSylwia Wnuczko status);
383230f3d53SJan Sokolowski return -EIO;
38465c275e4SSylwia Wnuczko }
385ff924657SSylwia Wnuczko
386ff924657SSylwia Wnuczko offset = ptr_value + module_offset + specific_ptr +
387ff924657SSylwia Wnuczko data_offset;
388ff924657SSylwia Wnuczko
389ff924657SSylwia Wnuczko status = i40e_read_nvm_buffer(hw, offset, &words_data_size,
390ff924657SSylwia Wnuczko data_ptr);
39165c275e4SSylwia Wnuczko if (status) {
39265c275e4SSylwia Wnuczko i40e_debug(hw, I40E_DEBUG_ALL,
39365c275e4SSylwia Wnuczko "Reading nvm buffer failed.Error code: %d.\n",
39465c275e4SSylwia Wnuczko status);
39565c275e4SSylwia Wnuczko }
39665c275e4SSylwia Wnuczko }
39765c275e4SSylwia Wnuczko
39865c275e4SSylwia Wnuczko return status;
39965c275e4SSylwia Wnuczko }
40065c275e4SSylwia Wnuczko
40165c275e4SSylwia Wnuczko /**
402d1bbe0eaSKamil Krawczyk * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
403d1bbe0eaSKamil Krawczyk * @hw: pointer to the HW structure
404d1bbe0eaSKamil Krawczyk * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
405d1bbe0eaSKamil Krawczyk * @words: (in) number of words to read; (out) number of words actually read
406d1bbe0eaSKamil Krawczyk * @data: words read from the Shadow RAM
407d1bbe0eaSKamil Krawczyk *
408d1bbe0eaSKamil Krawczyk * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
409d1bbe0eaSKamil Krawczyk * method. The buffer read is preceded by the NVM ownership take
410d1bbe0eaSKamil Krawczyk * and followed by the release.
411d1bbe0eaSKamil Krawczyk **/
i40e_read_nvm_buffer_srctl(struct i40e_hw * hw,u16 offset,u16 * words,u16 * data)4125180ff13SJan Sokolowski static int i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
413d1bbe0eaSKamil Krawczyk u16 *words, u16 *data)
414d1bbe0eaSKamil Krawczyk {
4155180ff13SJan Sokolowski int ret_code = 0;
416d1bbe0eaSKamil Krawczyk u16 index, word;
417d1bbe0eaSKamil Krawczyk
418d1bbe0eaSKamil Krawczyk /* Loop thru the selected region */
419d1bbe0eaSKamil Krawczyk for (word = 0; word < *words; word++) {
420d1bbe0eaSKamil Krawczyk index = offset + word;
421d1bbe0eaSKamil Krawczyk ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
422d1bbe0eaSKamil Krawczyk if (ret_code)
423d1bbe0eaSKamil Krawczyk break;
424d1bbe0eaSKamil Krawczyk }
425d1bbe0eaSKamil Krawczyk
426d1bbe0eaSKamil Krawczyk /* Update the number of words read from the Shadow RAM */
427d1bbe0eaSKamil Krawczyk *words = word;
428d1bbe0eaSKamil Krawczyk
429d1bbe0eaSKamil Krawczyk return ret_code;
430d1bbe0eaSKamil Krawczyk }
431d1bbe0eaSKamil Krawczyk
432d1bbe0eaSKamil Krawczyk /**
4337073f46eSShannon Nelson * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
4347073f46eSShannon Nelson * @hw: pointer to the HW structure
4357073f46eSShannon Nelson * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
4367073f46eSShannon Nelson * @words: (in) number of words to read; (out) number of words actually read
4377073f46eSShannon Nelson * @data: words read from the Shadow RAM
4387073f46eSShannon Nelson *
4397073f46eSShannon Nelson * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
4407073f46eSShannon Nelson * method. The buffer read is preceded by the NVM ownership take
4417073f46eSShannon Nelson * and followed by the release.
4427073f46eSShannon Nelson **/
i40e_read_nvm_buffer_aq(struct i40e_hw * hw,u16 offset,u16 * words,u16 * data)4435180ff13SJan Sokolowski static int i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
4447073f46eSShannon Nelson u16 *words, u16 *data)
4457073f46eSShannon Nelson {
4467073f46eSShannon Nelson bool last_cmd = false;
4477073f46eSShannon Nelson u16 words_read = 0;
4485180ff13SJan Sokolowski u16 read_size;
4495180ff13SJan Sokolowski int ret_code;
4507073f46eSShannon Nelson u16 i = 0;
4517073f46eSShannon Nelson
4527073f46eSShannon Nelson do {
4537073f46eSShannon Nelson /* Calculate number of bytes we should read in this step.
4547073f46eSShannon Nelson * FVL AQ do not allow to read more than one page at a time or
4557073f46eSShannon Nelson * to cross page boundaries.
4567073f46eSShannon Nelson */
4577073f46eSShannon Nelson if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
4587073f46eSShannon Nelson read_size = min(*words,
4597073f46eSShannon Nelson (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
4607073f46eSShannon Nelson (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
4617073f46eSShannon Nelson else
4627073f46eSShannon Nelson read_size = min((*words - words_read),
4637073f46eSShannon Nelson I40E_SR_SECTOR_SIZE_IN_WORDS);
4647073f46eSShannon Nelson
4657073f46eSShannon Nelson /* Check if this is last command, if so set proper flag */
4667073f46eSShannon Nelson if ((words_read + read_size) >= *words)
4677073f46eSShannon Nelson last_cmd = true;
4687073f46eSShannon Nelson
4697073f46eSShannon Nelson ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
4707073f46eSShannon Nelson data + words_read, last_cmd);
4717073f46eSShannon Nelson if (ret_code)
4727073f46eSShannon Nelson goto read_nvm_buffer_aq_exit;
4737073f46eSShannon Nelson
4747073f46eSShannon Nelson /* Increment counter for words already read and move offset to
4757073f46eSShannon Nelson * new read location
4767073f46eSShannon Nelson */
4777073f46eSShannon Nelson words_read += read_size;
4787073f46eSShannon Nelson offset += read_size;
4797073f46eSShannon Nelson } while (words_read < *words);
4807073f46eSShannon Nelson
4817073f46eSShannon Nelson for (i = 0; i < *words; i++)
4827073f46eSShannon Nelson data[i] = le16_to_cpu(((__le16 *)data)[i]);
4837073f46eSShannon Nelson
4847073f46eSShannon Nelson read_nvm_buffer_aq_exit:
4857073f46eSShannon Nelson *words = words_read;
4867073f46eSShannon Nelson return ret_code;
4877073f46eSShannon Nelson }
4887073f46eSShannon Nelson
4897073f46eSShannon Nelson /**
49009f79fd4SAnjali Singhai Jain * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock
4913e26186dSShannon Nelson * @hw: pointer to the HW structure
49256a62fc8SJesse Brandeburg * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
4933e26186dSShannon Nelson * @words: (in) number of words to read; (out) number of words actually read
4943e26186dSShannon Nelson * @data: words read from the Shadow RAM
49556a62fc8SJesse Brandeburg *
49656a62fc8SJesse Brandeburg * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
49709f79fd4SAnjali Singhai Jain * method.
49856a62fc8SJesse Brandeburg **/
__i40e_read_nvm_buffer(struct i40e_hw * hw,u16 offset,u16 * words,u16 * data)4995180ff13SJan Sokolowski static int __i40e_read_nvm_buffer(struct i40e_hw *hw,
50009f79fd4SAnjali Singhai Jain u16 offset, u16 *words,
50109f79fd4SAnjali Singhai Jain u16 *data)
50256a62fc8SJesse Brandeburg {
50309f79fd4SAnjali Singhai Jain if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
5042c4d36b7SStefano Brivio return i40e_read_nvm_buffer_aq(hw, offset, words, data);
5052c4d36b7SStefano Brivio
5062c4d36b7SStefano Brivio return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
50756a62fc8SJesse Brandeburg }
50856a62fc8SJesse Brandeburg
50956a62fc8SJesse Brandeburg /**
51065c275e4SSylwia Wnuczko * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acquire lock if necessary
51165c275e4SSylwia Wnuczko * @hw: pointer to the HW structure
51265c275e4SSylwia Wnuczko * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
51365c275e4SSylwia Wnuczko * @words: (in) number of words to read; (out) number of words actually read
51465c275e4SSylwia Wnuczko * @data: words read from the Shadow RAM
51565c275e4SSylwia Wnuczko *
51665c275e4SSylwia Wnuczko * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
51765c275e4SSylwia Wnuczko * method. The buffer read is preceded by the NVM ownership take
51865c275e4SSylwia Wnuczko * and followed by the release.
51965c275e4SSylwia Wnuczko **/
i40e_read_nvm_buffer(struct i40e_hw * hw,u16 offset,u16 * words,u16 * data)5205180ff13SJan Sokolowski int i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
52165c275e4SSylwia Wnuczko u16 *words, u16 *data)
52265c275e4SSylwia Wnuczko {
5235180ff13SJan Sokolowski int ret_code = 0;
52465c275e4SSylwia Wnuczko
52565c275e4SSylwia Wnuczko if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
52665c275e4SSylwia Wnuczko ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
52765c275e4SSylwia Wnuczko if (!ret_code) {
52865c275e4SSylwia Wnuczko ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
52965c275e4SSylwia Wnuczko data);
53065c275e4SSylwia Wnuczko i40e_release_nvm(hw);
53165c275e4SSylwia Wnuczko }
53265c275e4SSylwia Wnuczko } else {
53365c275e4SSylwia Wnuczko ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
53465c275e4SSylwia Wnuczko }
53565c275e4SSylwia Wnuczko
53665c275e4SSylwia Wnuczko return ret_code;
53765c275e4SSylwia Wnuczko }
53865c275e4SSylwia Wnuczko
53965c275e4SSylwia Wnuczko /**
540cd552cb4SShannon Nelson * i40e_write_nvm_aq - Writes Shadow RAM.
541cd552cb4SShannon Nelson * @hw: pointer to the HW structure.
542cd552cb4SShannon Nelson * @module_pointer: module pointer location in words from the NVM beginning
543cd552cb4SShannon Nelson * @offset: offset in words from module start
544cd552cb4SShannon Nelson * @words: number of words to write
545cd552cb4SShannon Nelson * @data: buffer with words to write to the Shadow RAM
546cd552cb4SShannon Nelson * @last_command: tells the AdminQ that this is the last command
547cd552cb4SShannon Nelson *
548cd552cb4SShannon Nelson * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
549cd552cb4SShannon Nelson **/
i40e_write_nvm_aq(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 words,void * data,bool last_command)5505180ff13SJan Sokolowski static int i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
551cd552cb4SShannon Nelson u32 offset, u16 words, void *data,
552cd552cb4SShannon Nelson bool last_command)
553cd552cb4SShannon Nelson {
5546b5c1b89SShannon Nelson struct i40e_asq_cmd_details cmd_details;
555230f3d53SJan Sokolowski int ret_code = -EIO;
5566b5c1b89SShannon Nelson
5576b5c1b89SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details));
5586b5c1b89SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc;
559cd552cb4SShannon Nelson
560cd552cb4SShannon Nelson /* Here we are checking the SR limit only for the flat memory model.
561cd552cb4SShannon Nelson * We cannot do it for the module-based model, as we did not acquire
562cd552cb4SShannon Nelson * the NVM resource yet (we cannot get the module pointer value).
563cd552cb4SShannon Nelson * Firmware will check the module-based model.
564cd552cb4SShannon Nelson */
565cd552cb4SShannon Nelson if ((offset + words) > hw->nvm.sr_size)
56674d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
56774d0d0edSShannon Nelson "NVM write error: offset %d beyond Shadow RAM limit %d\n",
56874d0d0edSShannon Nelson (offset + words), hw->nvm.sr_size);
569cd552cb4SShannon Nelson else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
570cd552cb4SShannon Nelson /* We can write only up to 4KB (one sector), in one AQ write */
57174d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
57274d0d0edSShannon Nelson "NVM write fail error: tried to write %d words, limit is %d.\n",
57374d0d0edSShannon Nelson words, I40E_SR_SECTOR_SIZE_IN_WORDS);
574cd552cb4SShannon Nelson else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
575cd552cb4SShannon Nelson != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
576cd552cb4SShannon Nelson /* A single write cannot spread over two sectors */
57774d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
57874d0d0edSShannon Nelson "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
57974d0d0edSShannon Nelson offset, words);
580cd552cb4SShannon Nelson else
581cd552cb4SShannon Nelson ret_code = i40e_aq_update_nvm(hw, module_pointer,
582cd552cb4SShannon Nelson 2 * offset, /*bytes*/
583cd552cb4SShannon Nelson 2 * words, /*bytes*/
584e3a5d6e6SPawel Jablonski data, last_command, 0,
585e3a5d6e6SPawel Jablonski &cmd_details);
586cd552cb4SShannon Nelson
587cd552cb4SShannon Nelson return ret_code;
588cd552cb4SShannon Nelson }
589cd552cb4SShannon Nelson
590cd552cb4SShannon Nelson /**
59156a62fc8SJesse Brandeburg * i40e_calc_nvm_checksum - Calculates and returns the checksum
59256a62fc8SJesse Brandeburg * @hw: pointer to hardware structure
59398d44381SJeff Kirsher * @checksum: pointer to the checksum
59456a62fc8SJesse Brandeburg *
5953e26186dSShannon Nelson * This function calculates SW Checksum that covers the whole 64kB shadow RAM
59656a62fc8SJesse Brandeburg * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
59756a62fc8SJesse Brandeburg * is customer specific and unknown. Therefore, this function skips all maximum
59856a62fc8SJesse Brandeburg * possible size of VPD (1kB).
59956a62fc8SJesse Brandeburg **/
i40e_calc_nvm_checksum(struct i40e_hw * hw,u16 * checksum)6005180ff13SJan Sokolowski static int i40e_calc_nvm_checksum(struct i40e_hw *hw,
60156a62fc8SJesse Brandeburg u16 *checksum)
60256a62fc8SJesse Brandeburg {
603d1bbe0eaSKamil Krawczyk struct i40e_virt_mem vmem;
60456a62fc8SJesse Brandeburg u16 pcie_alt_module = 0;
60556a62fc8SJesse Brandeburg u16 checksum_local = 0;
60656a62fc8SJesse Brandeburg u16 vpd_module = 0;
6075180ff13SJan Sokolowski int ret_code;
608d1bbe0eaSKamil Krawczyk u16 *data;
609d1bbe0eaSKamil Krawczyk u16 i = 0;
610d1bbe0eaSKamil Krawczyk
611d1bbe0eaSKamil Krawczyk ret_code = i40e_allocate_virt_mem(hw, &vmem,
612d1bbe0eaSKamil Krawczyk I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
613d1bbe0eaSKamil Krawczyk if (ret_code)
614d1bbe0eaSKamil Krawczyk goto i40e_calc_nvm_checksum_exit;
615d1bbe0eaSKamil Krawczyk data = (u16 *)vmem.va;
61656a62fc8SJesse Brandeburg
61756a62fc8SJesse Brandeburg /* read pointer to VPD area */
61809f79fd4SAnjali Singhai Jain ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
61956a62fc8SJesse Brandeburg if (ret_code) {
620230f3d53SJan Sokolowski ret_code = -EIO;
62156a62fc8SJesse Brandeburg goto i40e_calc_nvm_checksum_exit;
62256a62fc8SJesse Brandeburg }
62356a62fc8SJesse Brandeburg
62456a62fc8SJesse Brandeburg /* read pointer to PCIe Alt Auto-load module */
62509f79fd4SAnjali Singhai Jain ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
62656a62fc8SJesse Brandeburg &pcie_alt_module);
62756a62fc8SJesse Brandeburg if (ret_code) {
628230f3d53SJan Sokolowski ret_code = -EIO;
62956a62fc8SJesse Brandeburg goto i40e_calc_nvm_checksum_exit;
63056a62fc8SJesse Brandeburg }
63156a62fc8SJesse Brandeburg
63256a62fc8SJesse Brandeburg /* Calculate SW checksum that covers the whole 64kB shadow RAM
63356a62fc8SJesse Brandeburg * except the VPD and PCIe ALT Auto-load modules
63456a62fc8SJesse Brandeburg */
63556a62fc8SJesse Brandeburg for (i = 0; i < hw->nvm.sr_size; i++) {
636d1bbe0eaSKamil Krawczyk /* Read SR page */
637d1bbe0eaSKamil Krawczyk if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
638d1bbe0eaSKamil Krawczyk u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
63956a62fc8SJesse Brandeburg
64009f79fd4SAnjali Singhai Jain ret_code = __i40e_read_nvm_buffer(hw, i, &words, data);
64156a62fc8SJesse Brandeburg if (ret_code) {
642230f3d53SJan Sokolowski ret_code = -EIO;
64356a62fc8SJesse Brandeburg goto i40e_calc_nvm_checksum_exit;
64456a62fc8SJesse Brandeburg }
645d1bbe0eaSKamil Krawczyk }
646d1bbe0eaSKamil Krawczyk
647d1bbe0eaSKamil Krawczyk /* Skip Checksum word */
648d1bbe0eaSKamil Krawczyk if (i == I40E_SR_SW_CHECKSUM_WORD)
649d1bbe0eaSKamil Krawczyk continue;
650d1bbe0eaSKamil Krawczyk /* Skip VPD module (convert byte size to word count) */
651d1bbe0eaSKamil Krawczyk if ((i >= (u32)vpd_module) &&
652d1bbe0eaSKamil Krawczyk (i < ((u32)vpd_module +
653d1bbe0eaSKamil Krawczyk (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
654d1bbe0eaSKamil Krawczyk continue;
655d1bbe0eaSKamil Krawczyk }
656d1bbe0eaSKamil Krawczyk /* Skip PCIe ALT module (convert byte size to word count) */
657d1bbe0eaSKamil Krawczyk if ((i >= (u32)pcie_alt_module) &&
658d1bbe0eaSKamil Krawczyk (i < ((u32)pcie_alt_module +
659d1bbe0eaSKamil Krawczyk (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
660d1bbe0eaSKamil Krawczyk continue;
661d1bbe0eaSKamil Krawczyk }
662d1bbe0eaSKamil Krawczyk
663d1bbe0eaSKamil Krawczyk checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
66456a62fc8SJesse Brandeburg }
66556a62fc8SJesse Brandeburg
66656a62fc8SJesse Brandeburg *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
66756a62fc8SJesse Brandeburg
66856a62fc8SJesse Brandeburg i40e_calc_nvm_checksum_exit:
669d1bbe0eaSKamil Krawczyk i40e_free_virt_mem(hw, &vmem);
67056a62fc8SJesse Brandeburg return ret_code;
67156a62fc8SJesse Brandeburg }
67256a62fc8SJesse Brandeburg
67356a62fc8SJesse Brandeburg /**
674cd552cb4SShannon Nelson * i40e_update_nvm_checksum - Updates the NVM checksum
675cd552cb4SShannon Nelson * @hw: pointer to hardware structure
676cd552cb4SShannon Nelson *
677cd552cb4SShannon Nelson * NVM ownership must be acquired before calling this function and released
678cd552cb4SShannon Nelson * on ARQ completion event reception by caller.
679cd552cb4SShannon Nelson * This function will commit SR to NVM.
680cd552cb4SShannon Nelson **/
i40e_update_nvm_checksum(struct i40e_hw * hw)6815180ff13SJan Sokolowski int i40e_update_nvm_checksum(struct i40e_hw *hw)
682cd552cb4SShannon Nelson {
683dd38c583SJesse Brandeburg __le16 le_sum;
6845180ff13SJan Sokolowski int ret_code;
6855180ff13SJan Sokolowski u16 checksum;
686cd552cb4SShannon Nelson
687cd552cb4SShannon Nelson ret_code = i40e_calc_nvm_checksum(hw, &checksum);
688ad739d08STom Rix if (!ret_code) {
689dd38c583SJesse Brandeburg le_sum = cpu_to_le16(checksum);
690cd552cb4SShannon Nelson ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
691dd38c583SJesse Brandeburg 1, &le_sum, true);
692ad739d08STom Rix }
693cd552cb4SShannon Nelson
694cd552cb4SShannon Nelson return ret_code;
695cd552cb4SShannon Nelson }
696cd552cb4SShannon Nelson
697cd552cb4SShannon Nelson /**
69856a62fc8SJesse Brandeburg * i40e_validate_nvm_checksum - Validate EEPROM checksum
69956a62fc8SJesse Brandeburg * @hw: pointer to hardware structure
70056a62fc8SJesse Brandeburg * @checksum: calculated checksum
70156a62fc8SJesse Brandeburg *
70256a62fc8SJesse Brandeburg * Performs checksum calculation and validates the NVM SW checksum. If the
70356a62fc8SJesse Brandeburg * caller does not need checksum, the value can be NULL.
70456a62fc8SJesse Brandeburg **/
i40e_validate_nvm_checksum(struct i40e_hw * hw,u16 * checksum)7055180ff13SJan Sokolowski int i40e_validate_nvm_checksum(struct i40e_hw *hw,
70656a62fc8SJesse Brandeburg u16 *checksum)
70756a62fc8SJesse Brandeburg {
708e15c9fa0SJesse Brandeburg u16 checksum_local = 0;
7095180ff13SJan Sokolowski u16 checksum_sr = 0;
7105180ff13SJan Sokolowski int ret_code = 0;
71156a62fc8SJesse Brandeburg
71209f79fd4SAnjali Singhai Jain /* We must acquire the NVM lock in order to correctly synchronize the
71309f79fd4SAnjali Singhai Jain * NVM accesses across multiple PFs. Without doing so it is possible
71409f79fd4SAnjali Singhai Jain * for one of the PFs to read invalid data potentially indicating that
71509f79fd4SAnjali Singhai Jain * the checksum is invalid.
71656a62fc8SJesse Brandeburg */
71709f79fd4SAnjali Singhai Jain ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
71809f79fd4SAnjali Singhai Jain if (ret_code)
71909f79fd4SAnjali Singhai Jain return ret_code;
72009f79fd4SAnjali Singhai Jain ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
72109f79fd4SAnjali Singhai Jain __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
72209f79fd4SAnjali Singhai Jain i40e_release_nvm(hw);
72309f79fd4SAnjali Singhai Jain if (ret_code)
72409f79fd4SAnjali Singhai Jain return ret_code;
72556a62fc8SJesse Brandeburg
72656a62fc8SJesse Brandeburg /* Verify read checksum from EEPROM is the same as
72756a62fc8SJesse Brandeburg * calculated checksum
72856a62fc8SJesse Brandeburg */
72956a62fc8SJesse Brandeburg if (checksum_local != checksum_sr)
730230f3d53SJan Sokolowski ret_code = -EIO;
73156a62fc8SJesse Brandeburg
73256a62fc8SJesse Brandeburg /* If the user cares, return the calculated checksum */
73356a62fc8SJesse Brandeburg if (checksum)
73456a62fc8SJesse Brandeburg *checksum = checksum_local;
73556a62fc8SJesse Brandeburg
73656a62fc8SJesse Brandeburg return ret_code;
73756a62fc8SJesse Brandeburg }
738cd552cb4SShannon Nelson
7395180ff13SJan Sokolowski static int i40e_nvmupd_state_init(struct i40e_hw *hw,
740cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
74179afe839SShannon Nelson u8 *bytes, int *perrno);
7425180ff13SJan Sokolowski static int i40e_nvmupd_state_reading(struct i40e_hw *hw,
743cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
74479afe839SShannon Nelson u8 *bytes, int *perrno);
7455180ff13SJan Sokolowski static int i40e_nvmupd_state_writing(struct i40e_hw *hw,
746cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
747cd552cb4SShannon Nelson u8 *bytes, int *errno);
748cd552cb4SShannon Nelson static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
749cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
75079afe839SShannon Nelson int *perrno);
7515180ff13SJan Sokolowski static int i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
752cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
75379afe839SShannon Nelson int *perrno);
7545180ff13SJan Sokolowski static int i40e_nvmupd_nvm_write(struct i40e_hw *hw,
755cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
75679afe839SShannon Nelson u8 *bytes, int *perrno);
7575180ff13SJan Sokolowski static int i40e_nvmupd_nvm_read(struct i40e_hw *hw,
758cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
75979afe839SShannon Nelson u8 *bytes, int *perrno);
7605180ff13SJan Sokolowski static int i40e_nvmupd_exec_aq(struct i40e_hw *hw,
761e4c83c20SShannon Nelson struct i40e_nvm_access *cmd,
762e4c83c20SShannon Nelson u8 *bytes, int *perrno);
7635180ff13SJan Sokolowski static int i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
764b72dc7b1SShannon Nelson struct i40e_nvm_access *cmd,
765b72dc7b1SShannon Nelson u8 *bytes, int *perrno);
7665180ff13SJan Sokolowski static int i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
767e3a5d6e6SPawel Jablonski struct i40e_nvm_access *cmd,
768e3a5d6e6SPawel Jablonski u8 *bytes, int *perrno);
i40e_nvmupd_get_module(u32 val)769cd552cb4SShannon Nelson static inline u8 i40e_nvmupd_get_module(u32 val)
770cd552cb4SShannon Nelson {
771cd552cb4SShannon Nelson return (u8)(val & I40E_NVM_MOD_PNT_MASK);
772cd552cb4SShannon Nelson }
i40e_nvmupd_get_transaction(u32 val)773cd552cb4SShannon Nelson static inline u8 i40e_nvmupd_get_transaction(u32 val)
774cd552cb4SShannon Nelson {
775cd552cb4SShannon Nelson return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
776cd552cb4SShannon Nelson }
777cd552cb4SShannon Nelson
i40e_nvmupd_get_preservation_flags(u32 val)778e3a5d6e6SPawel Jablonski static inline u8 i40e_nvmupd_get_preservation_flags(u32 val)
779e3a5d6e6SPawel Jablonski {
780e3a5d6e6SPawel Jablonski return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >>
781e3a5d6e6SPawel Jablonski I40E_NVM_PRESERVATION_FLAGS_SHIFT);
782e3a5d6e6SPawel Jablonski }
783e3a5d6e6SPawel Jablonski
7844e68adfeSJingjing Wu static const char * const i40e_nvm_update_state_str[] = {
78574d0d0edSShannon Nelson "I40E_NVMUPD_INVALID",
78674d0d0edSShannon Nelson "I40E_NVMUPD_READ_CON",
78774d0d0edSShannon Nelson "I40E_NVMUPD_READ_SNT",
78874d0d0edSShannon Nelson "I40E_NVMUPD_READ_LCB",
78974d0d0edSShannon Nelson "I40E_NVMUPD_READ_SA",
79074d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_ERA",
79174d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_CON",
79274d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_SNT",
79374d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_LCB",
79474d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_SA",
79574d0d0edSShannon Nelson "I40E_NVMUPD_CSUM_CON",
79674d0d0edSShannon Nelson "I40E_NVMUPD_CSUM_SA",
79774d0d0edSShannon Nelson "I40E_NVMUPD_CSUM_LCB",
7980af8e9dbSShannon Nelson "I40E_NVMUPD_STATUS",
799e4c83c20SShannon Nelson "I40E_NVMUPD_EXEC_AQ",
800b72dc7b1SShannon Nelson "I40E_NVMUPD_GET_AQ_RESULT",
801e3a5d6e6SPawel Jablonski "I40E_NVMUPD_GET_AQ_EVENT",
80274d0d0edSShannon Nelson };
80374d0d0edSShannon Nelson
804cd552cb4SShannon Nelson /**
805cd552cb4SShannon Nelson * i40e_nvmupd_command - Process an NVM update command
806cd552cb4SShannon Nelson * @hw: pointer to hardware structure
807cd552cb4SShannon Nelson * @cmd: pointer to nvm update command
808cd552cb4SShannon Nelson * @bytes: pointer to the data buffer
80979afe839SShannon Nelson * @perrno: pointer to return error code
810cd552cb4SShannon Nelson *
811cd552cb4SShannon Nelson * Dispatches command depending on what update state is current
812cd552cb4SShannon Nelson **/
i40e_nvmupd_command(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)8135180ff13SJan Sokolowski int i40e_nvmupd_command(struct i40e_hw *hw,
814cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
81579afe839SShannon Nelson u8 *bytes, int *perrno)
816cd552cb4SShannon Nelson {
8170af8e9dbSShannon Nelson enum i40e_nvmupd_cmd upd_cmd;
8185180ff13SJan Sokolowski int status;
819cd552cb4SShannon Nelson
820cd552cb4SShannon Nelson /* assume success */
82179afe839SShannon Nelson *perrno = 0;
822cd552cb4SShannon Nelson
8230af8e9dbSShannon Nelson /* early check for status command and debug msgs */
8240af8e9dbSShannon Nelson upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
8250af8e9dbSShannon Nelson
826fed2db99SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n",
8270af8e9dbSShannon Nelson i40e_nvm_update_state_str[upd_cmd],
8280af8e9dbSShannon Nelson hw->nvmupd_state,
829fed2db99SShannon Nelson hw->nvm_release_on_done, hw->nvm_wait_opcode,
8301d73b2dbSShannon Nelson cmd->command, cmd->config, cmd->offset, cmd->data_size);
8310af8e9dbSShannon Nelson
8320af8e9dbSShannon Nelson if (upd_cmd == I40E_NVMUPD_INVALID) {
8330af8e9dbSShannon Nelson *perrno = -EFAULT;
8340af8e9dbSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
8350af8e9dbSShannon Nelson "i40e_nvmupd_validate_command returns %d errno %d\n",
8360af8e9dbSShannon Nelson upd_cmd, *perrno);
8370af8e9dbSShannon Nelson }
8380af8e9dbSShannon Nelson
8390af8e9dbSShannon Nelson /* a status request returns immediately rather than
8400af8e9dbSShannon Nelson * going into the state machine
8410af8e9dbSShannon Nelson */
8420af8e9dbSShannon Nelson if (upd_cmd == I40E_NVMUPD_STATUS) {
843fed2db99SShannon Nelson if (!cmd->data_size) {
844fed2db99SShannon Nelson *perrno = -EFAULT;
845230f3d53SJan Sokolowski return -EINVAL;
846fed2db99SShannon Nelson }
847fed2db99SShannon Nelson
8480af8e9dbSShannon Nelson bytes[0] = hw->nvmupd_state;
849fed2db99SShannon Nelson
850fed2db99SShannon Nelson if (cmd->data_size >= 4) {
851fed2db99SShannon Nelson bytes[1] = 0;
852fed2db99SShannon Nelson *((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
853fed2db99SShannon Nelson }
854fed2db99SShannon Nelson
85581fa7c97SMaciej Sosin /* Clear error status on read */
85681fa7c97SMaciej Sosin if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
85781fa7c97SMaciej Sosin hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
85881fa7c97SMaciej Sosin
8590af8e9dbSShannon Nelson return 0;
8600af8e9dbSShannon Nelson }
8610af8e9dbSShannon Nelson
86281fa7c97SMaciej Sosin /* Clear status even it is not read and log */
86381fa7c97SMaciej Sosin if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
86481fa7c97SMaciej Sosin i40e_debug(hw, I40E_DEBUG_NVM,
86581fa7c97SMaciej Sosin "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
86681fa7c97SMaciej Sosin hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
86781fa7c97SMaciej Sosin }
86881fa7c97SMaciej Sosin
8692bf01935SSudheer Mogilappagari /* Acquire lock to prevent race condition where adminq_task
8702bf01935SSudheer Mogilappagari * can execute after i40e_nvmupd_nvm_read/write but before state
871167d52edSSudheer Mogilappagari * variables (nvm_wait_opcode, nvm_release_on_done) are updated.
872167d52edSSudheer Mogilappagari *
873167d52edSSudheer Mogilappagari * During NVMUpdate, it is observed that lock could be held for
874167d52edSSudheer Mogilappagari * ~5ms for most commands. However lock is held for ~60ms for
875167d52edSSudheer Mogilappagari * NVMUPD_CSUM_LCB command.
8762bf01935SSudheer Mogilappagari */
8772bf01935SSudheer Mogilappagari mutex_lock(&hw->aq.arq_mutex);
878cd552cb4SShannon Nelson switch (hw->nvmupd_state) {
879cd552cb4SShannon Nelson case I40E_NVMUPD_STATE_INIT:
88079afe839SShannon Nelson status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
881cd552cb4SShannon Nelson break;
882cd552cb4SShannon Nelson
883cd552cb4SShannon Nelson case I40E_NVMUPD_STATE_READING:
88479afe839SShannon Nelson status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
885cd552cb4SShannon Nelson break;
886cd552cb4SShannon Nelson
887cd552cb4SShannon Nelson case I40E_NVMUPD_STATE_WRITING:
88879afe839SShannon Nelson status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
889cd552cb4SShannon Nelson break;
890cd552cb4SShannon Nelson
8912f1b5bc8SShannon Nelson case I40E_NVMUPD_STATE_INIT_WAIT:
8922f1b5bc8SShannon Nelson case I40E_NVMUPD_STATE_WRITE_WAIT:
893fed2db99SShannon Nelson /* if we need to stop waiting for an event, clear
894fed2db99SShannon Nelson * the wait info and return before doing anything else
895fed2db99SShannon Nelson */
896fed2db99SShannon Nelson if (cmd->offset == 0xffff) {
897e3a5d6e6SPawel Jablonski i40e_nvmupd_clear_wait_state(hw);
898167d52edSSudheer Mogilappagari status = 0;
899e3a5d6e6SPawel Jablonski break;
900fed2db99SShannon Nelson }
901fed2db99SShannon Nelson
902230f3d53SJan Sokolowski status = -EBUSY;
9032f1b5bc8SShannon Nelson *perrno = -EBUSY;
9042f1b5bc8SShannon Nelson break;
9052f1b5bc8SShannon Nelson
906cd552cb4SShannon Nelson default:
907cd552cb4SShannon Nelson /* invalid state, should never happen */
90874d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
90974d0d0edSShannon Nelson "NVMUPD: no such state %d\n", hw->nvmupd_state);
910230f3d53SJan Sokolowski status = -EOPNOTSUPP;
91179afe839SShannon Nelson *perrno = -ESRCH;
912cd552cb4SShannon Nelson break;
913cd552cb4SShannon Nelson }
914e3a5d6e6SPawel Jablonski
9152bf01935SSudheer Mogilappagari mutex_unlock(&hw->aq.arq_mutex);
916cd552cb4SShannon Nelson return status;
917cd552cb4SShannon Nelson }
918cd552cb4SShannon Nelson
919cd552cb4SShannon Nelson /**
920cd552cb4SShannon Nelson * i40e_nvmupd_state_init - Handle NVM update state Init
921cd552cb4SShannon Nelson * @hw: pointer to hardware structure
922cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer
923cd552cb4SShannon Nelson * @bytes: pointer to the data buffer
92479afe839SShannon Nelson * @perrno: pointer to return error code
925cd552cb4SShannon Nelson *
926cd552cb4SShannon Nelson * Process legitimate commands of the Init state and conditionally set next
927cd552cb4SShannon Nelson * state. Reject all other commands.
928cd552cb4SShannon Nelson **/
i40e_nvmupd_state_init(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)9295180ff13SJan Sokolowski static int i40e_nvmupd_state_init(struct i40e_hw *hw,
930cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
93179afe839SShannon Nelson u8 *bytes, int *perrno)
932cd552cb4SShannon Nelson {
933cd552cb4SShannon Nelson enum i40e_nvmupd_cmd upd_cmd;
9345180ff13SJan Sokolowski int status = 0;
935cd552cb4SShannon Nelson
93679afe839SShannon Nelson upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
937cd552cb4SShannon Nelson
938cd552cb4SShannon Nelson switch (upd_cmd) {
939cd552cb4SShannon Nelson case I40E_NVMUPD_READ_SA:
940cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
941cd552cb4SShannon Nelson if (status) {
94279afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status,
943bf848f32SShannon Nelson hw->aq.asq_last_status);
944cd552cb4SShannon Nelson } else {
94579afe839SShannon Nelson status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
946cd552cb4SShannon Nelson i40e_release_nvm(hw);
947cd552cb4SShannon Nelson }
948cd552cb4SShannon Nelson break;
949cd552cb4SShannon Nelson
950cd552cb4SShannon Nelson case I40E_NVMUPD_READ_SNT:
951cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
952cd552cb4SShannon Nelson if (status) {
95379afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status,
954bf848f32SShannon Nelson hw->aq.asq_last_status);
955cd552cb4SShannon Nelson } else {
95679afe839SShannon Nelson status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
9570fdd052cSShannon Nelson if (status)
9580fdd052cSShannon Nelson i40e_release_nvm(hw);
9590fdd052cSShannon Nelson else
960cd552cb4SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
961cd552cb4SShannon Nelson }
962cd552cb4SShannon Nelson break;
963cd552cb4SShannon Nelson
964cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_ERA:
965cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
966cd552cb4SShannon Nelson if (status) {
96779afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status,
968bf848f32SShannon Nelson hw->aq.asq_last_status);
969cd552cb4SShannon Nelson } else {
97079afe839SShannon Nelson status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
9712f1b5bc8SShannon Nelson if (status) {
972cd552cb4SShannon Nelson i40e_release_nvm(hw);
9732f1b5bc8SShannon Nelson } else {
974437f82a2SShannon Nelson hw->nvm_release_on_done = true;
975fed2db99SShannon Nelson hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase;
9762f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
9772f1b5bc8SShannon Nelson }
978cd552cb4SShannon Nelson }
979cd552cb4SShannon Nelson break;
980cd552cb4SShannon Nelson
981cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_SA:
982cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
983cd552cb4SShannon Nelson if (status) {
98479afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status,
985bf848f32SShannon Nelson hw->aq.asq_last_status);
986cd552cb4SShannon Nelson } else {
98779afe839SShannon Nelson status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
9882f1b5bc8SShannon Nelson if (status) {
989cd552cb4SShannon Nelson i40e_release_nvm(hw);
9902f1b5bc8SShannon Nelson } else {
991437f82a2SShannon Nelson hw->nvm_release_on_done = true;
992fed2db99SShannon Nelson hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
9932f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
9942f1b5bc8SShannon Nelson }
995cd552cb4SShannon Nelson }
996cd552cb4SShannon Nelson break;
997cd552cb4SShannon Nelson
998cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_SNT:
999cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1000cd552cb4SShannon Nelson if (status) {
100179afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status,
1002bf848f32SShannon Nelson hw->aq.asq_last_status);
1003cd552cb4SShannon Nelson } else {
100479afe839SShannon Nelson status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1005fed2db99SShannon Nelson if (status) {
10060fdd052cSShannon Nelson i40e_release_nvm(hw);
1007fed2db99SShannon Nelson } else {
1008fed2db99SShannon Nelson hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
10092f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1010cd552cb4SShannon Nelson }
1011fed2db99SShannon Nelson }
1012cd552cb4SShannon Nelson break;
1013cd552cb4SShannon Nelson
1014cd552cb4SShannon Nelson case I40E_NVMUPD_CSUM_SA:
1015cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1016cd552cb4SShannon Nelson if (status) {
101779afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status,
1018bf848f32SShannon Nelson hw->aq.asq_last_status);
1019cd552cb4SShannon Nelson } else {
1020cd552cb4SShannon Nelson status = i40e_update_nvm_checksum(hw);
1021cd552cb4SShannon Nelson if (status) {
102279afe839SShannon Nelson *perrno = hw->aq.asq_last_status ?
1023bf848f32SShannon Nelson i40e_aq_rc_to_posix(status,
1024bf848f32SShannon Nelson hw->aq.asq_last_status) :
1025cd552cb4SShannon Nelson -EIO;
1026cd552cb4SShannon Nelson i40e_release_nvm(hw);
1027cd552cb4SShannon Nelson } else {
1028437f82a2SShannon Nelson hw->nvm_release_on_done = true;
1029fed2db99SShannon Nelson hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
10302f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1031cd552cb4SShannon Nelson }
1032cd552cb4SShannon Nelson }
1033cd552cb4SShannon Nelson break;
1034cd552cb4SShannon Nelson
1035e4c83c20SShannon Nelson case I40E_NVMUPD_EXEC_AQ:
1036e4c83c20SShannon Nelson status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
1037e4c83c20SShannon Nelson break;
1038e4c83c20SShannon Nelson
1039b72dc7b1SShannon Nelson case I40E_NVMUPD_GET_AQ_RESULT:
1040b72dc7b1SShannon Nelson status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
1041b72dc7b1SShannon Nelson break;
1042b72dc7b1SShannon Nelson
1043e3a5d6e6SPawel Jablonski case I40E_NVMUPD_GET_AQ_EVENT:
1044e3a5d6e6SPawel Jablonski status = i40e_nvmupd_get_aq_event(hw, cmd, bytes, perrno);
1045e3a5d6e6SPawel Jablonski break;
1046e3a5d6e6SPawel Jablonski
1047cd552cb4SShannon Nelson default:
104874d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
104974d0d0edSShannon Nelson "NVMUPD: bad cmd %s in init state\n",
105074d0d0edSShannon Nelson i40e_nvm_update_state_str[upd_cmd]);
1051230f3d53SJan Sokolowski status = -EIO;
105279afe839SShannon Nelson *perrno = -ESRCH;
1053cd552cb4SShannon Nelson break;
1054cd552cb4SShannon Nelson }
1055cd552cb4SShannon Nelson return status;
1056cd552cb4SShannon Nelson }
1057cd552cb4SShannon Nelson
1058cd552cb4SShannon Nelson /**
1059cd552cb4SShannon Nelson * i40e_nvmupd_state_reading - Handle NVM update state Reading
1060cd552cb4SShannon Nelson * @hw: pointer to hardware structure
1061cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer
1062cd552cb4SShannon Nelson * @bytes: pointer to the data buffer
106379afe839SShannon Nelson * @perrno: pointer to return error code
1064cd552cb4SShannon Nelson *
1065cd552cb4SShannon Nelson * NVM ownership is already held. Process legitimate commands and set any
1066cd552cb4SShannon Nelson * change in state; reject all other commands.
1067cd552cb4SShannon Nelson **/
i40e_nvmupd_state_reading(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)10685180ff13SJan Sokolowski static int i40e_nvmupd_state_reading(struct i40e_hw *hw,
1069cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
107079afe839SShannon Nelson u8 *bytes, int *perrno)
1071cd552cb4SShannon Nelson {
1072cd552cb4SShannon Nelson enum i40e_nvmupd_cmd upd_cmd;
10735180ff13SJan Sokolowski int status = 0;
1074cd552cb4SShannon Nelson
107579afe839SShannon Nelson upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1076cd552cb4SShannon Nelson
1077cd552cb4SShannon Nelson switch (upd_cmd) {
1078cd552cb4SShannon Nelson case I40E_NVMUPD_READ_SA:
1079cd552cb4SShannon Nelson case I40E_NVMUPD_READ_CON:
108079afe839SShannon Nelson status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
1081cd552cb4SShannon Nelson break;
1082cd552cb4SShannon Nelson
1083cd552cb4SShannon Nelson case I40E_NVMUPD_READ_LCB:
108479afe839SShannon Nelson status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
1085cd552cb4SShannon Nelson i40e_release_nvm(hw);
1086cd552cb4SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1087cd552cb4SShannon Nelson break;
1088cd552cb4SShannon Nelson
1089cd552cb4SShannon Nelson default:
109074d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
109174d0d0edSShannon Nelson "NVMUPD: bad cmd %s in reading state.\n",
109274d0d0edSShannon Nelson i40e_nvm_update_state_str[upd_cmd]);
1093230f3d53SJan Sokolowski status = -EOPNOTSUPP;
109479afe839SShannon Nelson *perrno = -ESRCH;
1095cd552cb4SShannon Nelson break;
1096cd552cb4SShannon Nelson }
1097cd552cb4SShannon Nelson return status;
1098cd552cb4SShannon Nelson }
1099cd552cb4SShannon Nelson
1100cd552cb4SShannon Nelson /**
1101cd552cb4SShannon Nelson * i40e_nvmupd_state_writing - Handle NVM update state Writing
1102cd552cb4SShannon Nelson * @hw: pointer to hardware structure
1103cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer
1104cd552cb4SShannon Nelson * @bytes: pointer to the data buffer
110579afe839SShannon Nelson * @perrno: pointer to return error code
1106cd552cb4SShannon Nelson *
1107cd552cb4SShannon Nelson * NVM ownership is already held. Process legitimate commands and set any
1108cd552cb4SShannon Nelson * change in state; reject all other commands
1109cd552cb4SShannon Nelson **/
i40e_nvmupd_state_writing(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)11105180ff13SJan Sokolowski static int i40e_nvmupd_state_writing(struct i40e_hw *hw,
1111cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
111279afe839SShannon Nelson u8 *bytes, int *perrno)
1113cd552cb4SShannon Nelson {
1114cd552cb4SShannon Nelson enum i40e_nvmupd_cmd upd_cmd;
11152c47e351SShannon Nelson bool retry_attempt = false;
11165180ff13SJan Sokolowski int status = 0;
1117cd552cb4SShannon Nelson
111879afe839SShannon Nelson upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1119cd552cb4SShannon Nelson
11202c47e351SShannon Nelson retry:
1121cd552cb4SShannon Nelson switch (upd_cmd) {
1122cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_CON:
112379afe839SShannon Nelson status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1124fed2db99SShannon Nelson if (!status) {
1125fed2db99SShannon Nelson hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
11262f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1127fed2db99SShannon Nelson }
1128cd552cb4SShannon Nelson break;
1129cd552cb4SShannon Nelson
1130cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_LCB:
113179afe839SShannon Nelson status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
11322f1b5bc8SShannon Nelson if (status) {
11332f1b5bc8SShannon Nelson *perrno = hw->aq.asq_last_status ?
11342f1b5bc8SShannon Nelson i40e_aq_rc_to_posix(status,
11352f1b5bc8SShannon Nelson hw->aq.asq_last_status) :
11362f1b5bc8SShannon Nelson -EIO;
1137cd552cb4SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
11382f1b5bc8SShannon Nelson } else {
1139437f82a2SShannon Nelson hw->nvm_release_on_done = true;
1140fed2db99SShannon Nelson hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
11412f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
11422f1b5bc8SShannon Nelson }
1143cd552cb4SShannon Nelson break;
1144cd552cb4SShannon Nelson
1145cd552cb4SShannon Nelson case I40E_NVMUPD_CSUM_CON:
114609f79fd4SAnjali Singhai Jain /* Assumes the caller has acquired the nvm */
1147cd552cb4SShannon Nelson status = i40e_update_nvm_checksum(hw);
1148cd552cb4SShannon Nelson if (status) {
114979afe839SShannon Nelson *perrno = hw->aq.asq_last_status ?
1150bf848f32SShannon Nelson i40e_aq_rc_to_posix(status,
1151bf848f32SShannon Nelson hw->aq.asq_last_status) :
1152cd552cb4SShannon Nelson -EIO;
1153cd552cb4SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
11542f1b5bc8SShannon Nelson } else {
1155fed2db99SShannon Nelson hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
11562f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1157cd552cb4SShannon Nelson }
1158cd552cb4SShannon Nelson break;
1159cd552cb4SShannon Nelson
11600fdd052cSShannon Nelson case I40E_NVMUPD_CSUM_LCB:
116109f79fd4SAnjali Singhai Jain /* Assumes the caller has acquired the nvm */
11620fdd052cSShannon Nelson status = i40e_update_nvm_checksum(hw);
11632f1b5bc8SShannon Nelson if (status) {
116479afe839SShannon Nelson *perrno = hw->aq.asq_last_status ?
1165bf848f32SShannon Nelson i40e_aq_rc_to_posix(status,
1166bf848f32SShannon Nelson hw->aq.asq_last_status) :
11670fdd052cSShannon Nelson -EIO;
11680fdd052cSShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
11692f1b5bc8SShannon Nelson } else {
1170437f82a2SShannon Nelson hw->nvm_release_on_done = true;
1171fed2db99SShannon Nelson hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
11722f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
11732f1b5bc8SShannon Nelson }
11740fdd052cSShannon Nelson break;
11750fdd052cSShannon Nelson
1176cd552cb4SShannon Nelson default:
117774d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
117874d0d0edSShannon Nelson "NVMUPD: bad cmd %s in writing state.\n",
117974d0d0edSShannon Nelson i40e_nvm_update_state_str[upd_cmd]);
1180230f3d53SJan Sokolowski status = -EOPNOTSUPP;
118179afe839SShannon Nelson *perrno = -ESRCH;
1182cd552cb4SShannon Nelson break;
1183cd552cb4SShannon Nelson }
11842c47e351SShannon Nelson
11852c47e351SShannon Nelson /* In some circumstances, a multi-write transaction takes longer
11862c47e351SShannon Nelson * than the default 3 minute timeout on the write semaphore. If
11872c47e351SShannon Nelson * the write failed with an EBUSY status, this is likely the problem,
11882c47e351SShannon Nelson * so here we try to reacquire the semaphore then retry the write.
11892c47e351SShannon Nelson * We only do one retry, then give up.
11902c47e351SShannon Nelson */
11912c47e351SShannon Nelson if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
11922c47e351SShannon Nelson !retry_attempt) {
11932c47e351SShannon Nelson u32 old_asq_status = hw->aq.asq_last_status;
11945180ff13SJan Sokolowski int old_status = status;
11952c47e351SShannon Nelson u32 gtime;
11962c47e351SShannon Nelson
11972c47e351SShannon Nelson gtime = rd32(hw, I40E_GLVFGEN_TIMER);
11982c47e351SShannon Nelson if (gtime >= hw->nvm.hw_semaphore_timeout) {
11992c47e351SShannon Nelson i40e_debug(hw, I40E_DEBUG_ALL,
12002c47e351SShannon Nelson "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
12012c47e351SShannon Nelson gtime, hw->nvm.hw_semaphore_timeout);
12022c47e351SShannon Nelson i40e_release_nvm(hw);
12032c47e351SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
12042c47e351SShannon Nelson if (status) {
12052c47e351SShannon Nelson i40e_debug(hw, I40E_DEBUG_ALL,
12062c47e351SShannon Nelson "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
12072c47e351SShannon Nelson hw->aq.asq_last_status);
12082c47e351SShannon Nelson status = old_status;
12092c47e351SShannon Nelson hw->aq.asq_last_status = old_asq_status;
12102c47e351SShannon Nelson } else {
12112c47e351SShannon Nelson retry_attempt = true;
12122c47e351SShannon Nelson goto retry;
12132c47e351SShannon Nelson }
12142c47e351SShannon Nelson }
12152c47e351SShannon Nelson }
12162c47e351SShannon Nelson
1217cd552cb4SShannon Nelson return status;
1218cd552cb4SShannon Nelson }
1219cd552cb4SShannon Nelson
1220cd552cb4SShannon Nelson /**
1221e3a5d6e6SPawel Jablonski * i40e_nvmupd_clear_wait_state - clear wait state on hw
1222bab2fb60SShannon Nelson * @hw: pointer to the hardware structure
1223bab2fb60SShannon Nelson **/
i40e_nvmupd_clear_wait_state(struct i40e_hw * hw)1224e3a5d6e6SPawel Jablonski void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw)
1225bab2fb60SShannon Nelson {
1226bab2fb60SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
1227e3a5d6e6SPawel Jablonski "NVMUPD: clearing wait on opcode 0x%04x\n",
1228e3a5d6e6SPawel Jablonski hw->nvm_wait_opcode);
1229e3a5d6e6SPawel Jablonski
1230bab2fb60SShannon Nelson if (hw->nvm_release_on_done) {
1231bab2fb60SShannon Nelson i40e_release_nvm(hw);
1232bab2fb60SShannon Nelson hw->nvm_release_on_done = false;
1233bab2fb60SShannon Nelson }
1234fed2db99SShannon Nelson hw->nvm_wait_opcode = 0;
1235bab2fb60SShannon Nelson
123681fa7c97SMaciej Sosin if (hw->aq.arq_last_status) {
123781fa7c97SMaciej Sosin hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
123881fa7c97SMaciej Sosin return;
123981fa7c97SMaciej Sosin }
124081fa7c97SMaciej Sosin
1241bab2fb60SShannon Nelson switch (hw->nvmupd_state) {
1242bab2fb60SShannon Nelson case I40E_NVMUPD_STATE_INIT_WAIT:
1243bab2fb60SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1244bab2fb60SShannon Nelson break;
1245bab2fb60SShannon Nelson
1246bab2fb60SShannon Nelson case I40E_NVMUPD_STATE_WRITE_WAIT:
1247bab2fb60SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1248bab2fb60SShannon Nelson break;
1249bab2fb60SShannon Nelson
1250bab2fb60SShannon Nelson default:
1251bab2fb60SShannon Nelson break;
1252bab2fb60SShannon Nelson }
1253bab2fb60SShannon Nelson }
1254e3a5d6e6SPawel Jablonski
1255e3a5d6e6SPawel Jablonski /**
1256e3a5d6e6SPawel Jablonski * i40e_nvmupd_check_wait_event - handle NVM update operation events
1257e3a5d6e6SPawel Jablonski * @hw: pointer to the hardware structure
1258e3a5d6e6SPawel Jablonski * @opcode: the event that just happened
1259f5254429SJacob Keller * @desc: AdminQ descriptor
1260e3a5d6e6SPawel Jablonski **/
i40e_nvmupd_check_wait_event(struct i40e_hw * hw,u16 opcode,struct i40e_aq_desc * desc)1261e3a5d6e6SPawel Jablonski void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode,
1262e3a5d6e6SPawel Jablonski struct i40e_aq_desc *desc)
1263e3a5d6e6SPawel Jablonski {
1264e3a5d6e6SPawel Jablonski u32 aq_desc_len = sizeof(struct i40e_aq_desc);
1265e3a5d6e6SPawel Jablonski
1266e3a5d6e6SPawel Jablonski if (opcode == hw->nvm_wait_opcode) {
1267e3a5d6e6SPawel Jablonski memcpy(&hw->nvm_aq_event_desc, desc, aq_desc_len);
1268e3a5d6e6SPawel Jablonski i40e_nvmupd_clear_wait_state(hw);
1269e3a5d6e6SPawel Jablonski }
1270bab2fb60SShannon Nelson }
1271bab2fb60SShannon Nelson
1272bab2fb60SShannon Nelson /**
1273cd552cb4SShannon Nelson * i40e_nvmupd_validate_command - Validate given command
1274cd552cb4SShannon Nelson * @hw: pointer to hardware structure
1275cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer
127679afe839SShannon Nelson * @perrno: pointer to return error code
1277cd552cb4SShannon Nelson *
1278cd552cb4SShannon Nelson * Return one of the valid command types or I40E_NVMUPD_INVALID
1279cd552cb4SShannon Nelson **/
i40e_nvmupd_validate_command(struct i40e_hw * hw,struct i40e_nvm_access * cmd,int * perrno)1280cd552cb4SShannon Nelson static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1281cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
128279afe839SShannon Nelson int *perrno)
1283cd552cb4SShannon Nelson {
1284cd552cb4SShannon Nelson enum i40e_nvmupd_cmd upd_cmd;
12850af8e9dbSShannon Nelson u8 module, transaction;
1286cd552cb4SShannon Nelson
1287cd552cb4SShannon Nelson /* anything that doesn't match a recognized case is an error */
1288cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_INVALID;
1289cd552cb4SShannon Nelson
1290cd552cb4SShannon Nelson transaction = i40e_nvmupd_get_transaction(cmd->config);
12910af8e9dbSShannon Nelson module = i40e_nvmupd_get_module(cmd->config);
1292cd552cb4SShannon Nelson
1293cd552cb4SShannon Nelson /* limits on data size */
1294cd552cb4SShannon Nelson if ((cmd->data_size < 1) ||
1295cd552cb4SShannon Nelson (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
129674d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
129774d0d0edSShannon Nelson "i40e_nvmupd_validate_command data_size %d\n",
1298cd552cb4SShannon Nelson cmd->data_size);
129979afe839SShannon Nelson *perrno = -EFAULT;
1300cd552cb4SShannon Nelson return I40E_NVMUPD_INVALID;
1301cd552cb4SShannon Nelson }
1302cd552cb4SShannon Nelson
1303cd552cb4SShannon Nelson switch (cmd->command) {
1304cd552cb4SShannon Nelson case I40E_NVM_READ:
1305cd552cb4SShannon Nelson switch (transaction) {
1306cd552cb4SShannon Nelson case I40E_NVM_CON:
1307cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_READ_CON;
1308cd552cb4SShannon Nelson break;
1309cd552cb4SShannon Nelson case I40E_NVM_SNT:
1310cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_READ_SNT;
1311cd552cb4SShannon Nelson break;
1312cd552cb4SShannon Nelson case I40E_NVM_LCB:
1313cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_READ_LCB;
1314cd552cb4SShannon Nelson break;
1315cd552cb4SShannon Nelson case I40E_NVM_SA:
1316cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_READ_SA;
1317cd552cb4SShannon Nelson break;
13180af8e9dbSShannon Nelson case I40E_NVM_EXEC:
13190af8e9dbSShannon Nelson if (module == 0xf)
13200af8e9dbSShannon Nelson upd_cmd = I40E_NVMUPD_STATUS;
1321b72dc7b1SShannon Nelson else if (module == 0)
1322b72dc7b1SShannon Nelson upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
13230af8e9dbSShannon Nelson break;
1324e3a5d6e6SPawel Jablonski case I40E_NVM_AQE:
1325e3a5d6e6SPawel Jablonski upd_cmd = I40E_NVMUPD_GET_AQ_EVENT;
1326e3a5d6e6SPawel Jablonski break;
1327cd552cb4SShannon Nelson }
1328cd552cb4SShannon Nelson break;
1329cd552cb4SShannon Nelson
1330cd552cb4SShannon Nelson case I40E_NVM_WRITE:
1331cd552cb4SShannon Nelson switch (transaction) {
1332cd552cb4SShannon Nelson case I40E_NVM_CON:
1333cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_CON;
1334cd552cb4SShannon Nelson break;
1335cd552cb4SShannon Nelson case I40E_NVM_SNT:
1336cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_SNT;
1337cd552cb4SShannon Nelson break;
1338cd552cb4SShannon Nelson case I40E_NVM_LCB:
1339cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_LCB;
1340cd552cb4SShannon Nelson break;
1341cd552cb4SShannon Nelson case I40E_NVM_SA:
1342cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_SA;
1343cd552cb4SShannon Nelson break;
1344cd552cb4SShannon Nelson case I40E_NVM_ERA:
1345cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_ERA;
1346cd552cb4SShannon Nelson break;
1347cd552cb4SShannon Nelson case I40E_NVM_CSUM:
1348cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_CSUM_CON;
1349cd552cb4SShannon Nelson break;
1350cd552cb4SShannon Nelson case (I40E_NVM_CSUM|I40E_NVM_SA):
1351cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_CSUM_SA;
1352cd552cb4SShannon Nelson break;
1353cd552cb4SShannon Nelson case (I40E_NVM_CSUM|I40E_NVM_LCB):
1354cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_CSUM_LCB;
1355cd552cb4SShannon Nelson break;
1356e4c83c20SShannon Nelson case I40E_NVM_EXEC:
1357e4c83c20SShannon Nelson if (module == 0)
1358e4c83c20SShannon Nelson upd_cmd = I40E_NVMUPD_EXEC_AQ;
1359e4c83c20SShannon Nelson break;
1360cd552cb4SShannon Nelson }
1361cd552cb4SShannon Nelson break;
1362cd552cb4SShannon Nelson }
1363cd552cb4SShannon Nelson
1364cd552cb4SShannon Nelson return upd_cmd;
1365cd552cb4SShannon Nelson }
1366cd552cb4SShannon Nelson
1367cd552cb4SShannon Nelson /**
1368e4c83c20SShannon Nelson * i40e_nvmupd_exec_aq - Run an AQ command
1369e4c83c20SShannon Nelson * @hw: pointer to hardware structure
1370e4c83c20SShannon Nelson * @cmd: pointer to nvm update command buffer
1371e4c83c20SShannon Nelson * @bytes: pointer to the data buffer
1372e4c83c20SShannon Nelson * @perrno: pointer to return error code
1373e4c83c20SShannon Nelson *
1374e4c83c20SShannon Nelson * cmd structure contains identifiers and data buffer
1375e4c83c20SShannon Nelson **/
i40e_nvmupd_exec_aq(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)13765180ff13SJan Sokolowski static int i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1377e4c83c20SShannon Nelson struct i40e_nvm_access *cmd,
1378e4c83c20SShannon Nelson u8 *bytes, int *perrno)
1379e4c83c20SShannon Nelson {
1380e4c83c20SShannon Nelson struct i40e_asq_cmd_details cmd_details;
1381e4c83c20SShannon Nelson struct i40e_aq_desc *aq_desc;
1382e4c83c20SShannon Nelson u32 buff_size = 0;
1383e4c83c20SShannon Nelson u8 *buff = NULL;
1384e4c83c20SShannon Nelson u32 aq_desc_len;
1385e4c83c20SShannon Nelson u32 aq_data_len;
13865180ff13SJan Sokolowski int status;
1387e4c83c20SShannon Nelson
1388e4c83c20SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1389e3a5d6e6SPawel Jablonski if (cmd->offset == 0xffff)
1390e3a5d6e6SPawel Jablonski return 0;
1391e3a5d6e6SPawel Jablonski
1392e4c83c20SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details));
1393e4c83c20SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc;
1394e4c83c20SShannon Nelson
1395e4c83c20SShannon Nelson aq_desc_len = sizeof(struct i40e_aq_desc);
1396e4c83c20SShannon Nelson memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1397e4c83c20SShannon Nelson
1398e4c83c20SShannon Nelson /* get the aq descriptor */
1399e4c83c20SShannon Nelson if (cmd->data_size < aq_desc_len) {
1400e4c83c20SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
1401e4c83c20SShannon Nelson "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1402e4c83c20SShannon Nelson cmd->data_size, aq_desc_len);
1403e4c83c20SShannon Nelson *perrno = -EINVAL;
1404230f3d53SJan Sokolowski return -EINVAL;
1405e4c83c20SShannon Nelson }
1406e4c83c20SShannon Nelson aq_desc = (struct i40e_aq_desc *)bytes;
1407e4c83c20SShannon Nelson
1408e4c83c20SShannon Nelson /* if data buffer needed, make sure it's ready */
1409e4c83c20SShannon Nelson aq_data_len = cmd->data_size - aq_desc_len;
1410e4c83c20SShannon Nelson buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen));
1411e4c83c20SShannon Nelson if (buff_size) {
1412e4c83c20SShannon Nelson if (!hw->nvm_buff.va) {
1413e4c83c20SShannon Nelson status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1414e4c83c20SShannon Nelson hw->aq.asq_buf_size);
1415e4c83c20SShannon Nelson if (status)
1416e4c83c20SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
1417e4c83c20SShannon Nelson "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1418e4c83c20SShannon Nelson status);
1419e4c83c20SShannon Nelson }
1420e4c83c20SShannon Nelson
1421e4c83c20SShannon Nelson if (hw->nvm_buff.va) {
1422e4c83c20SShannon Nelson buff = hw->nvm_buff.va;
1423e4c83c20SShannon Nelson memcpy(buff, &bytes[aq_desc_len], aq_data_len);
1424e4c83c20SShannon Nelson }
1425e4c83c20SShannon Nelson }
1426e4c83c20SShannon Nelson
1427e3a5d6e6SPawel Jablonski if (cmd->offset)
1428e3a5d6e6SPawel Jablonski memset(&hw->nvm_aq_event_desc, 0, aq_desc_len);
1429e3a5d6e6SPawel Jablonski
1430e4c83c20SShannon Nelson /* and away we go! */
1431e4c83c20SShannon Nelson status = i40e_asq_send_command(hw, aq_desc, buff,
1432e4c83c20SShannon Nelson buff_size, &cmd_details);
1433e4c83c20SShannon Nelson if (status) {
1434e4c83c20SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
1435d5ba1842SJan Sokolowski "%s err %pe aq_err %s\n",
1436d5ba1842SJan Sokolowski __func__, ERR_PTR(status),
1437e4c83c20SShannon Nelson i40e_aq_str(hw, hw->aq.asq_last_status));
1438e4c83c20SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1439e3a5d6e6SPawel Jablonski return status;
1440e4c83c20SShannon Nelson }
1441e4c83c20SShannon Nelson
1442fed2db99SShannon Nelson /* should we wait for a followup event? */
1443fed2db99SShannon Nelson if (cmd->offset) {
1444fed2db99SShannon Nelson hw->nvm_wait_opcode = cmd->offset;
1445fed2db99SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1446fed2db99SShannon Nelson }
1447fed2db99SShannon Nelson
1448e4c83c20SShannon Nelson return status;
1449e4c83c20SShannon Nelson }
1450e4c83c20SShannon Nelson
1451e4c83c20SShannon Nelson /**
1452b72dc7b1SShannon Nelson * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1453b72dc7b1SShannon Nelson * @hw: pointer to hardware structure
1454b72dc7b1SShannon Nelson * @cmd: pointer to nvm update command buffer
1455b72dc7b1SShannon Nelson * @bytes: pointer to the data buffer
1456b72dc7b1SShannon Nelson * @perrno: pointer to return error code
1457b72dc7b1SShannon Nelson *
1458b72dc7b1SShannon Nelson * cmd structure contains identifiers and data buffer
1459b72dc7b1SShannon Nelson **/
i40e_nvmupd_get_aq_result(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)14605180ff13SJan Sokolowski static int i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1461b72dc7b1SShannon Nelson struct i40e_nvm_access *cmd,
1462b72dc7b1SShannon Nelson u8 *bytes, int *perrno)
1463b72dc7b1SShannon Nelson {
1464b72dc7b1SShannon Nelson u32 aq_total_len;
1465b72dc7b1SShannon Nelson u32 aq_desc_len;
1466b72dc7b1SShannon Nelson int remainder;
1467b72dc7b1SShannon Nelson u8 *buff;
1468b72dc7b1SShannon Nelson
1469b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1470b72dc7b1SShannon Nelson
1471b72dc7b1SShannon Nelson aq_desc_len = sizeof(struct i40e_aq_desc);
1472b72dc7b1SShannon Nelson aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen);
1473b72dc7b1SShannon Nelson
1474b72dc7b1SShannon Nelson /* check offset range */
1475b72dc7b1SShannon Nelson if (cmd->offset > aq_total_len) {
1476b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1477b72dc7b1SShannon Nelson __func__, cmd->offset, aq_total_len);
1478b72dc7b1SShannon Nelson *perrno = -EINVAL;
1479230f3d53SJan Sokolowski return -EINVAL;
1480b72dc7b1SShannon Nelson }
1481b72dc7b1SShannon Nelson
1482b72dc7b1SShannon Nelson /* check copylength range */
1483b72dc7b1SShannon Nelson if (cmd->data_size > (aq_total_len - cmd->offset)) {
1484b72dc7b1SShannon Nelson int new_len = aq_total_len - cmd->offset;
1485b72dc7b1SShannon Nelson
1486b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1487b72dc7b1SShannon Nelson __func__, cmd->data_size, new_len);
1488b72dc7b1SShannon Nelson cmd->data_size = new_len;
1489b72dc7b1SShannon Nelson }
1490b72dc7b1SShannon Nelson
1491b72dc7b1SShannon Nelson remainder = cmd->data_size;
1492b72dc7b1SShannon Nelson if (cmd->offset < aq_desc_len) {
1493b72dc7b1SShannon Nelson u32 len = aq_desc_len - cmd->offset;
1494b72dc7b1SShannon Nelson
1495b72dc7b1SShannon Nelson len = min(len, cmd->data_size);
1496b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1497b72dc7b1SShannon Nelson __func__, cmd->offset, cmd->offset + len);
1498b72dc7b1SShannon Nelson
1499b72dc7b1SShannon Nelson buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1500b72dc7b1SShannon Nelson memcpy(bytes, buff, len);
1501b72dc7b1SShannon Nelson
1502b72dc7b1SShannon Nelson bytes += len;
1503b72dc7b1SShannon Nelson remainder -= len;
1504b72dc7b1SShannon Nelson buff = hw->nvm_buff.va;
1505b72dc7b1SShannon Nelson } else {
1506b72dc7b1SShannon Nelson buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1507b72dc7b1SShannon Nelson }
1508b72dc7b1SShannon Nelson
1509b72dc7b1SShannon Nelson if (remainder > 0) {
1510b72dc7b1SShannon Nelson int start_byte = buff - (u8 *)hw->nvm_buff.va;
1511b72dc7b1SShannon Nelson
1512b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1513b72dc7b1SShannon Nelson __func__, start_byte, start_byte + remainder);
1514b72dc7b1SShannon Nelson memcpy(bytes, buff, remainder);
1515b72dc7b1SShannon Nelson }
1516b72dc7b1SShannon Nelson
1517b72dc7b1SShannon Nelson return 0;
1518b72dc7b1SShannon Nelson }
1519b72dc7b1SShannon Nelson
1520b72dc7b1SShannon Nelson /**
1521e3a5d6e6SPawel Jablonski * i40e_nvmupd_get_aq_event - Get the Admin Queue event from previous exec_aq
1522e3a5d6e6SPawel Jablonski * @hw: pointer to hardware structure
1523e3a5d6e6SPawel Jablonski * @cmd: pointer to nvm update command buffer
1524e3a5d6e6SPawel Jablonski * @bytes: pointer to the data buffer
1525e3a5d6e6SPawel Jablonski * @perrno: pointer to return error code
1526e3a5d6e6SPawel Jablonski *
1527e3a5d6e6SPawel Jablonski * cmd structure contains identifiers and data buffer
1528e3a5d6e6SPawel Jablonski **/
i40e_nvmupd_get_aq_event(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)15295180ff13SJan Sokolowski static int i40e_nvmupd_get_aq_event(struct i40e_hw *hw,
1530e3a5d6e6SPawel Jablonski struct i40e_nvm_access *cmd,
1531e3a5d6e6SPawel Jablonski u8 *bytes, int *perrno)
1532e3a5d6e6SPawel Jablonski {
1533e3a5d6e6SPawel Jablonski u32 aq_total_len;
1534e3a5d6e6SPawel Jablonski u32 aq_desc_len;
1535e3a5d6e6SPawel Jablonski
1536e3a5d6e6SPawel Jablonski i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1537e3a5d6e6SPawel Jablonski
1538e3a5d6e6SPawel Jablonski aq_desc_len = sizeof(struct i40e_aq_desc);
1539e3a5d6e6SPawel Jablonski aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_aq_event_desc.datalen);
1540e3a5d6e6SPawel Jablonski
1541e3a5d6e6SPawel Jablonski /* check copylength range */
1542e3a5d6e6SPawel Jablonski if (cmd->data_size > aq_total_len) {
1543e3a5d6e6SPawel Jablonski i40e_debug(hw, I40E_DEBUG_NVM,
1544e3a5d6e6SPawel Jablonski "%s: copy length %d too big, trimming to %d\n",
1545e3a5d6e6SPawel Jablonski __func__, cmd->data_size, aq_total_len);
1546e3a5d6e6SPawel Jablonski cmd->data_size = aq_total_len;
1547e3a5d6e6SPawel Jablonski }
1548e3a5d6e6SPawel Jablonski
1549e3a5d6e6SPawel Jablonski memcpy(bytes, &hw->nvm_aq_event_desc, cmd->data_size);
1550e3a5d6e6SPawel Jablonski
1551e3a5d6e6SPawel Jablonski return 0;
1552e3a5d6e6SPawel Jablonski }
1553e3a5d6e6SPawel Jablonski
1554e3a5d6e6SPawel Jablonski /**
1555cd552cb4SShannon Nelson * i40e_nvmupd_nvm_read - Read NVM
1556cd552cb4SShannon Nelson * @hw: pointer to hardware structure
1557cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer
1558cd552cb4SShannon Nelson * @bytes: pointer to the data buffer
155979afe839SShannon Nelson * @perrno: pointer to return error code
1560cd552cb4SShannon Nelson *
1561cd552cb4SShannon Nelson * cmd structure contains identifiers and data buffer
1562cd552cb4SShannon Nelson **/
i40e_nvmupd_nvm_read(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)15635180ff13SJan Sokolowski static int i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1564cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
156579afe839SShannon Nelson u8 *bytes, int *perrno)
1566cd552cb4SShannon Nelson {
15676b5c1b89SShannon Nelson struct i40e_asq_cmd_details cmd_details;
1568cd552cb4SShannon Nelson u8 module, transaction;
15695180ff13SJan Sokolowski int status;
1570cd552cb4SShannon Nelson bool last;
1571cd552cb4SShannon Nelson
1572cd552cb4SShannon Nelson transaction = i40e_nvmupd_get_transaction(cmd->config);
1573cd552cb4SShannon Nelson module = i40e_nvmupd_get_module(cmd->config);
1574cd552cb4SShannon Nelson last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1575cd552cb4SShannon Nelson
15766b5c1b89SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details));
15776b5c1b89SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc;
15786b5c1b89SShannon Nelson
1579cd552cb4SShannon Nelson status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
15806b5c1b89SShannon Nelson bytes, last, &cmd_details);
158174d0d0edSShannon Nelson if (status) {
158274d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
158374d0d0edSShannon Nelson "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
158474d0d0edSShannon Nelson module, cmd->offset, cmd->data_size);
158574d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
158674d0d0edSShannon Nelson "i40e_nvmupd_nvm_read status %d aq %d\n",
158774d0d0edSShannon Nelson status, hw->aq.asq_last_status);
158879afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
158974d0d0edSShannon Nelson }
1590cd552cb4SShannon Nelson
1591cd552cb4SShannon Nelson return status;
1592cd552cb4SShannon Nelson }
1593cd552cb4SShannon Nelson
1594cd552cb4SShannon Nelson /**
1595cd552cb4SShannon Nelson * i40e_nvmupd_nvm_erase - Erase an NVM module
1596cd552cb4SShannon Nelson * @hw: pointer to hardware structure
1597cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer
159879afe839SShannon Nelson * @perrno: pointer to return error code
1599cd552cb4SShannon Nelson *
1600cd552cb4SShannon Nelson * module, offset, data_size and data are in cmd structure
1601cd552cb4SShannon Nelson **/
i40e_nvmupd_nvm_erase(struct i40e_hw * hw,struct i40e_nvm_access * cmd,int * perrno)16025180ff13SJan Sokolowski static int i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1603cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
160479afe839SShannon Nelson int *perrno)
1605cd552cb4SShannon Nelson {
16066b5c1b89SShannon Nelson struct i40e_asq_cmd_details cmd_details;
1607cd552cb4SShannon Nelson u8 module, transaction;
16085180ff13SJan Sokolowski int status = 0;
1609cd552cb4SShannon Nelson bool last;
1610cd552cb4SShannon Nelson
1611cd552cb4SShannon Nelson transaction = i40e_nvmupd_get_transaction(cmd->config);
1612cd552cb4SShannon Nelson module = i40e_nvmupd_get_module(cmd->config);
1613cd552cb4SShannon Nelson last = (transaction & I40E_NVM_LCB);
16146b5c1b89SShannon Nelson
16156b5c1b89SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details));
16166b5c1b89SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc;
16176b5c1b89SShannon Nelson
1618cd552cb4SShannon Nelson status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
16196b5c1b89SShannon Nelson last, &cmd_details);
162074d0d0edSShannon Nelson if (status) {
162174d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
162274d0d0edSShannon Nelson "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
162374d0d0edSShannon Nelson module, cmd->offset, cmd->data_size);
162474d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
162574d0d0edSShannon Nelson "i40e_nvmupd_nvm_erase status %d aq %d\n",
162674d0d0edSShannon Nelson status, hw->aq.asq_last_status);
162779afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
162874d0d0edSShannon Nelson }
1629cd552cb4SShannon Nelson
1630cd552cb4SShannon Nelson return status;
1631cd552cb4SShannon Nelson }
1632cd552cb4SShannon Nelson
1633cd552cb4SShannon Nelson /**
1634cd552cb4SShannon Nelson * i40e_nvmupd_nvm_write - Write NVM
1635cd552cb4SShannon Nelson * @hw: pointer to hardware structure
1636cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer
1637cd552cb4SShannon Nelson * @bytes: pointer to the data buffer
163879afe839SShannon Nelson * @perrno: pointer to return error code
1639cd552cb4SShannon Nelson *
1640cd552cb4SShannon Nelson * module, offset, data_size and data are in cmd structure
1641cd552cb4SShannon Nelson **/
i40e_nvmupd_nvm_write(struct i40e_hw * hw,struct i40e_nvm_access * cmd,u8 * bytes,int * perrno)16425180ff13SJan Sokolowski static int i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1643cd552cb4SShannon Nelson struct i40e_nvm_access *cmd,
164479afe839SShannon Nelson u8 *bytes, int *perrno)
1645cd552cb4SShannon Nelson {
16466b5c1b89SShannon Nelson struct i40e_asq_cmd_details cmd_details;
1647cd552cb4SShannon Nelson u8 module, transaction;
1648e3a5d6e6SPawel Jablonski u8 preservation_flags;
16495180ff13SJan Sokolowski int status = 0;
1650cd552cb4SShannon Nelson bool last;
1651cd552cb4SShannon Nelson
1652cd552cb4SShannon Nelson transaction = i40e_nvmupd_get_transaction(cmd->config);
1653cd552cb4SShannon Nelson module = i40e_nvmupd_get_module(cmd->config);
1654cd552cb4SShannon Nelson last = (transaction & I40E_NVM_LCB);
1655e3a5d6e6SPawel Jablonski preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config);
165674d0d0edSShannon Nelson
16576b5c1b89SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details));
16586b5c1b89SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc;
16596b5c1b89SShannon Nelson
1660cd552cb4SShannon Nelson status = i40e_aq_update_nvm(hw, module, cmd->offset,
16616b5c1b89SShannon Nelson (u16)cmd->data_size, bytes, last,
1662e3a5d6e6SPawel Jablonski preservation_flags, &cmd_details);
166374d0d0edSShannon Nelson if (status) {
166474d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
166574d0d0edSShannon Nelson "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
166674d0d0edSShannon Nelson module, cmd->offset, cmd->data_size);
166774d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM,
166874d0d0edSShannon Nelson "i40e_nvmupd_nvm_write status %d aq %d\n",
166974d0d0edSShannon Nelson status, hw->aq.asq_last_status);
167079afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
167174d0d0edSShannon Nelson }
1672cd552cb4SShannon Nelson
1673cd552cb4SShannon Nelson return status;
1674cd552cb4SShannon Nelson }
1675