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Searched full:r2p0 (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcache-l2x0.h118 #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
119 #define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
120 #define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
125 #define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
130 #define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,scu.yaml19 Revision r2p0
23 Manial Revision r2p0
/openbmc/linux/arch/arm/mm/
H A Dcache-tauros3.h16 * but with PREFETCH_CTRL (r2p0) and an additional event counter.
H A Dproc-v7.S333 teq r6, #0x20 @ only present in r2p0
340 teq r6, #0x20 @ only present in r2p0
356 teq r6, #0x20 @ present in r2p0
H A DKconfig1032 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
H A Dcache-l2x0.c439 * 588369: PL310 R0P0->R1P0, fixed R2P0.
447 * 727915: PL310 R2P0->R3P0, fixed R3P1.
557 /* From r2p0, there is Prefetch offset/control register */ in l2c310_save()
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,global_timer.yaml22 description: driver supports versions r2p0 and above.
/openbmc/linux/arch/arm/kernel/
H A Dsmp_scu.c58 /* Cortex-A9 earlier than r2p0 has no standby bit in SCU */ in scu_enable()
/openbmc/linux/arch/arm64/kernel/
H A Dcpu_errata.c316 * - 1188873 affects r0p0 to r2p0
362 /* Cortex A76 r0p0 to r2p0 */
370 /* Cortex A55 r0p0 to r2p0 */
/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-impl.c115 * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before in arm_mmu500_reset()
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S258 cmp r2, #0x20 @ Applies to including and above R2p0
273 cmp r2, #0x20 @ Applies to including and above R2p0
/openbmc/linux/arch/arm/
H A DKconfig655 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
671 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
703 (r2p0..r2p2) erratum. Under certain conditions, specific to the
731 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
785 r2p0) erratum. The Store Buffer does not have any automatic draining
/openbmc/linux/drivers/spi/
H A Dspi-sprd-adi.c54 * ADI supports 12/14bit address for r2p0, and additional 17bit for r3p0 or
82 * REG_ADI_RD_CMD bit[14:0] for r2p0
/openbmc/linux/drivers/clocksource/
H A Darm_global_timer.c351 * In A9 r2p0 the comparators for each processor with the global timer in global_timer_of_register()
/openbmc/qemu/hw/timer/
H A Da9gtimer.c94 /* R2p0+, where the compare function is >= */ in a9_gtimer_update()
/openbmc/linux/arch/arm64/
H A DKconfig656 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
682 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c248 cpu->midr = 0x412FD050; /* r2p0 */ in aarch64_a55_initfn()