/openbmc/linux/drivers/media/pci/ttpci/ |
H A D | budget.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 9 * Copyright (C) 1999-2002 Ralph Metzler 47 struct saa7146_dev *dev=budget->dev; in Set22K() 58 struct saa7146_dev *dev=budget->dev; in DiseqcSendBit() 73 for (i=7; i>=0; i--) { in DiseqcSendByte() 84 struct saa7146_dev *dev=budget->dev; in SendDiSEqCMsg() 97 if (burst!=-1) { in SendDiSEqCMsg() 121 struct saa7146_dev *dev=budget->dev; in SetVoltage_Activy() 138 return -EINVAL; in SetVoltage_Activy() 147 struct budget *budget = fe->dvb->priv; in siemens_budget_set_voltage() [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | k3-am654-ddr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 8 compatible = "ti,am654-ddrss"; 12 reg-names = "ss", "ctl", "phy"; 14 power-domains = <&k3_pds 20>, 16 assigned-clocks = <&k3_clks 20 1>; 17 assigned-clock-rates = <DDR_PLL_FREQUENCY>; 18 u-boot,dm-spl; 20 ti,ctl-reg = < 42 ti,ctl-crc = < [all …]
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H A D | rk3188-radxarock.dts | 1 // SPDX-License-Identifier: GPL-2.0+ OR X11 6 /dts-v1/; 7 #include <dt-bindings/input/input.h> 9 #include "rk3188-radxarock-u-boot.dtsi" 16 /* stdout-path = &uart2; */ 17 stdout-path = "serial2:115200n8"; 21 u-boot,dm-pre-reloc; 22 u-boot,boot-led = "rock:red:power"; 30 gpio-keys { 31 compatible = "gpio-keys"; [all …]
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/openbmc/linux/sound/soc/codecs/ |
H A D | cs35l32.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * cs35l32.h -- CS35L32 ALSA SoC audio driver 36 #define CS35L32_PWRCTL1 0x06 /* Power Ctl 1 */ 37 #define CS35L32_PWRCTL2 0x07 /* Power Ctl 2 */ 38 #define CS35L32_CLK_CTL 0x08 /* Clock Ctl */ 41 #define CS35L32_BST_CPCP_CTL 0x0B /* Conv Peak Curr Protection CTL */ 43 #define CS35L32_AUDIO_LED_MNGR 0x0D /* Audio/LED Pwr Manager */ 45 #define CS35L32_CLASSD_CTL 0x10 /* Class D Amp CTL */ 46 #define CS35L32_PROTECT_CTL 0x11 /* Protection Release CTL */
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H A D | cs35l32.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * cs35l32.c -- CS35L32 ALSA SoC audio driver 27 #include <sound/soc-dapm.h> 30 #include <dt-bindings/sound/cs35l32.h> 51 { 0x06, 0x04 }, /* Power Ctl 1 */ 52 { 0x07, 0xE8 }, /* Power Ctl 2 */ 53 { 0x08, 0x40 }, /* Clock Ctl */ 56 { 0x0B, 0x40 }, /* Conv Peak Curr Protection CTL */ 58 { 0x0D, 0x03 }, /* Audio/LED Pwr Manager */ 60 { 0x10, 0x14 }, /* Class D Amp CTL */ [all …]
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H A D | cs42l56.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * cs42l56.c -- CS42L56 ALSA SoC audio driver 29 #include <sound/soc-dapm.h> 63 { 3, 0x7f }, /* r03 - Power Ctl 1 */ 64 { 4, 0xff }, /* r04 - Power Ctl 2 */ 65 { 5, 0x00 }, /* ro5 - Clocking Ctl 1 */ 66 { 6, 0x0b }, /* r06 - Clocking Ctl 2 */ 67 { 7, 0x00 }, /* r07 - Serial Format */ 68 { 8, 0x05 }, /* r08 - Class H Ctl */ 69 { 9, 0x0c }, /* r09 - Misc Ctl */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | nvidia,tegra194-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some 23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 29 - nvidia,tegra194-pcie-ep [all …]
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H A D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of 20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device 26 - nvidia,tegra194-pcie [all …]
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/openbmc/linux/sound/pci/ctxfi/ |
H A D | cthw20k1.c | 1 // SPDX-License-Identifier: GPL-2.0-only 76 * Fixed-point value in 8.24 format for parameter channel */ 82 u16 ctl:1; member 88 u16 czbfs:1; /* Clear Z-Buffers */ 95 unsigned int ctl; member 162 return -ENOMEM; in src_get_rsc_ctrl_blk() 178 struct src_rsc_ctrl_blk *ctl = blk; in src_set_state() local 180 set_field(&ctl->ctl, SRCCTL_STATE, state); in src_set_state() 181 ctl->dirty.bf.ctl = 1; in src_set_state() 187 struct src_rsc_ctrl_blk *ctl = blk; in src_set_bm() local [all …]
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/openbmc/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3288-rock2-square.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include "rk3288-rock2-som.dtsi" 9 compatible = "radxa,rock2-square", "rockchip,rk3288"; 12 stdout-path = "serial2:115200n8"; 15 adc-keys { 16 compatible = "adc-keys"; 17 io-channels = <&saradc 1>; 18 io-channel-names = "buttons"; [all …]
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H A D | rk3188-radxarock.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 7 #include <dt-bindings/input/input.h> 23 gpio-keys { 24 compatible = "gpio-keys"; 27 key-power { 31 linux,input-type = <1>; 32 wakeup-source; 33 debounce-interval = <100>; 37 gpio-leds { [all …]
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H A D | rk3188-bqedison2qc.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/i2c/i2c.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 14 model = "BQ Edison2 Quad-Core"; 15 compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; 29 compatible = "pwm-backlight"; 30 power-supply = <&vsys>; 34 gpio-keys { [all …]
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/openbmc/u-boot/drivers/ram/ |
H A D | k3-am654-ddrss.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 14 #include <power-domain.h> 18 #include "k3-am654-ddrss.h" 26 * struct am654_ddrss_desc - Description of ddrss integration. 60 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val) 61 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off) 69 * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete 93 return -EINVAL; in am654_ddrss_dram_wait_for_init_complt() 97 ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY)) in am654_ddrss_dram_wait_for_init_complt() [all …]
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/openbmc/linux/drivers/media/i2c/ |
H A D | tvp7002_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics 6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> 15 * ------------------ 19 * CTL: Control 30 * PWR: Power
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/openbmc/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra194.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra194-clock.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 8 #include <dt-bindings/power/tegra194-powergate.h> 9 #include <dt-bindings/reset/tegra194-reset.h> 10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h> [all …]
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H A D | tegra234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra234-clock.h> 4 #include <dt-bindings/gpio/tegra234-gpio.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/mailbox/tegra186-hsp.h> 7 #include <dt-bindings/memory/tegra234-mc.h> 8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9 #include <dt-bindings/power/tegra234-powergate.h> 10 #include <dt-bindings/reset/tegra234-reset.h> 11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h> [all …]
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/openbmc/linux/drivers/pcmcia/ |
H A D | tcic.c | 3 Device driver for Databook TCIC-2 PCMCIA controller 55 MODULE_DESCRIPTION("Databook TCIC-2 PCMCIA socket driver"); 62 /* The base port address of the TCIC-2 chip */ 66 static int ignore = -1; 76 /* The card status change interrupt -- 0 means autoselect */ 79 /* Poll status interval -- 0 means default to interrupt */ 82 /* Delay for card status double-checking */ 195 return 2*(ns-14)/cycle_time; in to_cycles() 214 return -1; in try_irq() 218 return -1; in try_irq() [all …]
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/openbmc/qemu/hw/alpha/ |
H A D | typhoon.c | 19 #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost" 20 #define TYPE_TYPHOON_IOMMU_MEMORY_REGION "typhoon-iommu-memory-region" 47 uint64_t ctl; member 64 /* If there are any non-masked interrupts, tell the cpu. */ in cpu_irq_change() 97 ret = s->cchip.misc | (cpu->cpu_index & 3); in cchip_read() 114 ret = s->cchip.dim[0]; in cchip_read() 118 ret = s->cchip.dim[1]; in cchip_read() 122 ret = s->cchip.dim[0] & s->cchip.drir; in cchip_read() 126 ret = s->cchip.dim[1] & s->cchip.drir; in cchip_read() 130 ret = s->cchip.drir; in cchip_read() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/ |
H A D | nvidia,tegra186-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 16 - nvidia,tegra186-pmc 17 - nvidia,tegra194-pmc 18 - nvidia,tegra234-pmc 24 reg-names: [all …]
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra30-cardhu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/thermal/thermal.h> 5 #include "tegra30-cpu-opp.dtsi" 6 #include "tegra30-cpu-opp-microvolt.dtsi" 16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use 17 * tegra30-cardhu-a04.dts. 20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th 22 * The (downstream internal) U-Boot of Cardhu display the board-id as 43 stdout-path = "serial0:115200n8"; [all …]
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/openbmc/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3368-r88.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include <dt-bindings/input/input.h> 20 stdout-path = "serial2:115200n8"; 28 emmc_pwrseq: emmc-pwrseq { 29 compatible = "mmc-pwrseq-emmc"; 30 pinctrl-0 = <&emmc_reset>; 31 pinctrl-names = "default"; 32 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; 35 keys: gpio-keys { [all …]
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H A D | rk3368-orion-r68-meta.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 7 #include <dt-bindings/input/input.h> 12 compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; 20 stdout-path = "serial2:115200n8"; 28 emmc_pwrseq: emmc-pwrseq { 29 compatible = "mmc-pwrseq-emmc"; 30 pinctrl-0 = <&emmc_reset>; 31 pinctrl-names = "default"; 32 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; [all …]
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/openbmc/linux/drivers/net/wireless/intel/iwlegacy/ |
H A D | 3945.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 #define IL3945_FW_PRE "iwlwifi-3945-" 41 * Use default noise value of -127 ... this is below the range of measurable 43 * Also, -127 works better than 0 when averaging frames with/without 47 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127) 49 /* Module parameters accessible from iwl-*.c */ 146 #define IL_INVALID_VALUE -1 160 x->u.rx_frame.stats.payload + \ [all …]
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/openbmc/linux/drivers/video/fbdev/matrox/ |
H A D | matroxfb_DAC1064.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz> 51 p = (1 << p) - 1; in DAC1064_calcclock() 94 DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p); in DAC1064_setpclk() 95 minfo->hw.DACclk[0] = m; in DAC1064_setpclk() 96 minfo->hw.DACclk[1] = n; in DAC1064_setpclk() 97 minfo->hw.DACclk[2] = p; in DAC1064_setpclk() 104 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_setmclk() 108 if (minfo->devflags.noinit) { in DAC1064_setmclk() 110 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); in DAC1064_setmclk() [all …]
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/openbmc/linux/drivers/net/wireless/ath/ath9k/ |
H A D | ar9003_eeprom.c | 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 30 /* Local defines to distinguish between extension and control CTL's */ 36 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 37 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 39 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) macro 67 * bit0 - enable tx temp comp - disabled 68 * bit1 - enable tx volt comp - disabled 69 * bit2 - enable fastClock - enabled 70 * bit3 - enable doubling - enabled 71 * bit4 - enable internal regulator - disabled [all …]
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