1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2eef5bb24SBrian Austin /* 3eef5bb24SBrian Austin * cs35l32.h -- CS35L32 ALSA SoC audio driver 4eef5bb24SBrian Austin * 5eef5bb24SBrian Austin * Copyright 2014 CirrusLogic, Inc. 6eef5bb24SBrian Austin * 7eef5bb24SBrian Austin * Author: Brian Austin <brian.austin@cirrus.com> 8eef5bb24SBrian Austin */ 9eef5bb24SBrian Austin 10eef5bb24SBrian Austin #ifndef __CS35L32_H__ 11eef5bb24SBrian Austin #define __CS35L32_H__ 12eef5bb24SBrian Austin 13eef5bb24SBrian Austin struct cs35l32_platform_data { 14eef5bb24SBrian Austin /* Low Battery Threshold */ 15eef5bb24SBrian Austin unsigned int batt_thresh; 16eef5bb24SBrian Austin /* Low Battery Recovery */ 17eef5bb24SBrian Austin unsigned int batt_recov; 18eef5bb24SBrian Austin /* LED Current Management*/ 19eef5bb24SBrian Austin unsigned int led_mng; 20eef5bb24SBrian Austin /* Audio Gain w/ LED */ 21eef5bb24SBrian Austin unsigned int audiogain_mng; 22eef5bb24SBrian Austin /* Boost Management */ 23eef5bb24SBrian Austin unsigned int boost_mng; 24eef5bb24SBrian Austin /* Data CFG for DUAL device */ 25eef5bb24SBrian Austin unsigned int sdout_datacfg; 26eef5bb24SBrian Austin /* SDOUT Sharing */ 27eef5bb24SBrian Austin unsigned int sdout_share; 28eef5bb24SBrian Austin }; 29eef5bb24SBrian Austin 30eef5bb24SBrian Austin #define CS35L32_CHIP_ID 0x00035A32 31eef5bb24SBrian Austin #define CS35L32_DEVID_AB 0x01 /* Device ID A & B [RO] */ 32eef5bb24SBrian Austin #define CS35L32_DEVID_CD 0x02 /* Device ID C & D [RO] */ 33eef5bb24SBrian Austin #define CS35L32_DEVID_E 0x03 /* Device ID E [RO] */ 34eef5bb24SBrian Austin #define CS35L32_FAB_ID 0x04 /* Fab ID [RO] */ 35eef5bb24SBrian Austin #define CS35L32_REV_ID 0x05 /* Revision ID [RO] */ 36eef5bb24SBrian Austin #define CS35L32_PWRCTL1 0x06 /* Power Ctl 1 */ 37eef5bb24SBrian Austin #define CS35L32_PWRCTL2 0x07 /* Power Ctl 2 */ 38eef5bb24SBrian Austin #define CS35L32_CLK_CTL 0x08 /* Clock Ctl */ 39eef5bb24SBrian Austin #define CS35L32_BATT_THRESHOLD 0x09 /* Low Battery Threshold */ 40eef5bb24SBrian Austin #define CS35L32_VMON 0x0A /* Voltage Monitor [RO] */ 41eef5bb24SBrian Austin #define CS35L32_BST_CPCP_CTL 0x0B /* Conv Peak Curr Protection CTL */ 42eef5bb24SBrian Austin #define CS35L32_IMON_SCALING 0x0C /* IMON Scaling */ 43eef5bb24SBrian Austin #define CS35L32_AUDIO_LED_MNGR 0x0D /* Audio/LED Pwr Manager */ 44eef5bb24SBrian Austin #define CS35L32_ADSP_CTL 0x0F /* Serial Port Control */ 45eef5bb24SBrian Austin #define CS35L32_CLASSD_CTL 0x10 /* Class D Amp CTL */ 46eef5bb24SBrian Austin #define CS35L32_PROTECT_CTL 0x11 /* Protection Release CTL */ 47eef5bb24SBrian Austin #define CS35L32_INT_MASK_1 0x12 /* Interrupt Mask 1 */ 48eef5bb24SBrian Austin #define CS35L32_INT_MASK_2 0x13 /* Interrupt Mask 2 */ 49eef5bb24SBrian Austin #define CS35L32_INT_MASK_3 0x14 /* Interrupt Mask 3 */ 50eef5bb24SBrian Austin #define CS35L32_INT_STATUS_1 0x15 /* Interrupt Status 1 [RO] */ 51eef5bb24SBrian Austin #define CS35L32_INT_STATUS_2 0x16 /* Interrupt Status 2 [RO] */ 52eef5bb24SBrian Austin #define CS35L32_INT_STATUS_3 0x17 /* Interrupt Status 3 [RO] */ 53eef5bb24SBrian Austin #define CS35L32_LED_STATUS 0x18 /* LED Lighting Status [RO] */ 54eef5bb24SBrian Austin #define CS35L32_FLASH_MODE 0x19 /* LED Flash Mode Current */ 55eef5bb24SBrian Austin #define CS35L32_MOVIE_MODE 0x1A /* LED Movie Mode Current */ 56eef5bb24SBrian Austin #define CS35L32_FLASH_TIMER 0x1B /* LED Flash Timer */ 57eef5bb24SBrian Austin #define CS35L32_FLASH_INHIBIT 0x1C /* LED Flash Inhibit Current */ 58eef5bb24SBrian Austin #define CS35L32_MAX_REGISTER 0x1C 59eef5bb24SBrian Austin 60eef5bb24SBrian Austin #define CS35L32_MCLK_DIV2 0x01 61eef5bb24SBrian Austin #define CS35L32_MCLK_RATIO 0x01 62eef5bb24SBrian Austin #define CS35L32_MCLKDIS 0x80 63eef5bb24SBrian Austin #define CS35L32_PDN_ALL 0x01 64eef5bb24SBrian Austin #define CS35L32_PDN_AMP 0x80 65eef5bb24SBrian Austin #define CS35L32_PDN_BOOST 0x04 66eef5bb24SBrian Austin #define CS35L32_PDN_IMON 0x40 67eef5bb24SBrian Austin #define CS35L32_PDN_VMON 0x80 68eef5bb24SBrian Austin #define CS35L32_PDN_VPMON 0x20 69eef5bb24SBrian Austin #define CS35L32_PDN_ADSP 0x08 70eef5bb24SBrian Austin 71eef5bb24SBrian Austin #define CS35L32_MCLK_DIV2_MASK 0x40 72eef5bb24SBrian Austin #define CS35L32_MCLK_RATIO_MASK 0x01 73eef5bb24SBrian Austin #define CS35L32_MCLK_MASK 0x41 74eef5bb24SBrian Austin #define CS35L32_ADSP_MASTER_MASK 0x40 75eef5bb24SBrian Austin #define CS35L32_BOOST_MASK 0x03 76eef5bb24SBrian Austin #define CS35L32_GAIN_MGR_MASK 0x08 77eef5bb24SBrian Austin #define CS35L32_ADSP_SHARE_MASK 0x08 78eef5bb24SBrian Austin #define CS35L32_ADSP_DATACFG_MASK 0x30 794c38b9c3SAxel Lin #define CS35L32_SDOUT_3ST 0x08 80eef5bb24SBrian Austin #define CS35L32_BATT_REC_MASK 0x0E 81eef5bb24SBrian Austin #define CS35L32_BATT_THRESH_MASK 0x30 82eef5bb24SBrian Austin 83eef5bb24SBrian Austin #define CS35L32_RATES (SNDRV_PCM_RATE_48000) 84eef5bb24SBrian Austin #define CS35L32_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 85eef5bb24SBrian Austin SNDRV_PCM_FMTBIT_S24_LE | \ 86eef5bb24SBrian Austin SNDRV_PCM_FMTBIT_S32_LE) 87eef5bb24SBrian Austin 88eef5bb24SBrian Austin 89eef5bb24SBrian Austin #endif 90