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/openbmc/qemu/linux-headers/linux/
H A Dpsci.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * ARM Power State and Coordination Interface (PSCI) header
5 * This header holds common PSCI defines and macros shared
16 * PSCI v0.1 interface
18 * The PSCI v0.1 function numbers are implementation defined.
20 * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
22 * to PSCI v0.1.
25 /* PSCI v0.2 interface */
34 #define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
44 #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
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/openbmc/u-boot/include/linux/
H A Dpsci.h2 * ARM Power State and Coordination Interface (PSCI) header
4 * This header holds common PSCI defines and macros shared
15 * PSCI v0.1 interface
17 * The PSCI v0.1 function numbers are implementation defined.
19 * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
21 * to PSCI v0.1.
24 /* PSCI v0.2 interface */
33 #define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
43 #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
49 /* PSCI v0.2 power state encoding for CPU_SUSPEND function */
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/openbmc/u-boot/arch/arm/dts/
H A Dthunderx-88xx.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Cavium Thunder DTS file - Thunder SoC description
10 compatible = "cavium,thunder-88xx";
11 interrupt-parent = <&gic0>;
12 #address-cells = <2>;
13 #size-cells = <2>;
15 psci {
16 compatible = "arm,psci-0.2";
21 #address-cells = <2>;
22 #size-cells = <0>;
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H A Dfsl-imx8-ca53.dtsi17 #address-cells = <2>;
18 #size-cells = <0>;
20 idle-states {
21 entry-method = "psci";
23 CPU_SLEEP: cpu-sleep {
24 compatible = "arm,idle-state";
25 local-timer-stop;
26 arm,psci-suspend-param = <0x0000000>;
27 entry-latency-us = <700>;
28 exit-latency-us = <250>;
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H A Dfsl-imx8-ca35.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8qxp-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <0>;
14 /* We have 1 clusters having 4 Cortex-A35 cores */
17 compatible = "arm,cortex-a35";
19 enable-method = "psci";
20 next-level-cache = <&A35_L2>;
23 A35_1: cpu@1 {
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H A Dhi6220.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/hi6220-clock.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 psci {
17 compatible = "arm,psci-0.2";
22 #address-cells = <2>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dsun50i-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <sunxi-h3-h5.dtsi>
47 #address-cells = <1>;
48 #size-cells = <0>;
51 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
57 cpu@1 {
58 compatible = "arm,cortex-a53", "arm,armv8";
60 reg = <1>;
61 enable-method = "psci";
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H A Dmeson-gxm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gxl.dtsi"
10 compatible = "amlogic,meson-gxm";
13 cpu-map {
47 compatible = "arm,cortex-a53", "arm,armv8";
49 enable-method = "psci";
50 next-level-cache = <&l2>;
51 clocks = <&scpi_dvfs 1>;
56 compatible = "arm,cortex-a53", "arm,armv8";
58 enable-method = "psci";
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H A Darmada-ap806-quad.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include "armada-ap806.dtsi"
51 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a72", "arm,armv8";
61 enable-method = "psci";
65 compatible = "arm,cortex-a72", "arm,armv8";
67 enable-method = "psci";
71 compatible = "arm,cortex-a72", "arm,armv8";
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H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
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H A Dk3-am65.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic500>;
16 #address-cells = <2>;
17 #size-cells = <2>;
31 compatible = "linaro,optee-tz";
35 psci: psci { label
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H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53", "arm,armv8";
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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0043-firmware-psci-Fix-bind_smccc_features-psci-check.patch4 Subject: [PATCH] firmware: psci: Fix bind_smccc_features psci check
6 Message-ID: <20240304144242.11666-2-o451686892@gmail.com> (raw)
7 In-Reply-To: <20240304144242.11666-1-o451686892@gmail.com>
9 According to PSCI specification DEN0022F, PSCI_FEATURES is used to check
12 Signed-off-by: Weizhao Ouyang <o451686892@gmail.com>
13 Signed-off-by: Bence Balogh <bence.balogh@arm.com>
14 Upstream-Status: Submitted [https://lore.kernel.org/all/20240304144242.11666-2-o451686892@gmail.com…
15 ---
16 drivers/firmware/psci.c | 5 ++++-
17 include/linux/arm-smccc.h | 6 ++++++
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H A D0029-corstone1000-enable-PSCI-reset.patch4 Subject: [PATCH] corstone1000: enable PSCI reset
6 Even though corstone1000 does not implement entire PSCI APIs,it relies on
7 PSCI reset interface for the system reset. U-boot change the config name, so we
10 Upstream-Status: Pending [Not submitted to upstream yet]
11 Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
12 ---
13 configs/corstone1000_defconfig | 3 ++-
14 1 file changed, 2 insertions(+), 1 deletion(-)
16 diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
18 --- a/configs/corstone1000_defconfig
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H A D0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch8 Upstream-Status: Submitted [https://lore.kernel.org/all/20240612100421.47938-1-harsimransingh.tunga…
9 Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
10 ---
11 arch/arm/dts/corstone1000-fvp.dts | 25 +++++++++++++++++++++++++
12 arch/arm/dts/corstone1000.dtsi | 2 +-
13 2 files changed, 26 insertions(+), 1 deletion(-)
15 diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
17 --- a/arch/arm/dts/corstone1000-fvp.dts
18 +++ b/arch/arm/dts/corstone1000-fvp.dts
19 @@ -49,3 +49,28 @@
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/openbmc/u-boot/drivers/firmware/
H A Dpsci.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on drivers/firmware/psci.c from Linux:
14 #include <linux/arm-smccc.h>
17 #include <linux/psci.h>
19 #define DRIVER_NAME "psci"
21 #define PSCI_METHOD_HVC 1
49 /* No SYSTEM_RESET support for PSCI 0.1 */ in psci_bind()
50 if (device_is_compatible(dev, "arm,psci-0.2") || in psci_bind()
51 device_is_compatible(dev, "arm,psci-1.0")) { in psci_bind()
54 /* bind psci-sysreset optionally */ in psci_bind()
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/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dpsci.S1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
10 #include <asm/psci.h>
12 /* Default PSCI function, return -1, Not Implemented */
20 /* PSCI function and ID table definition*/
27 /* 32 bits PSCI default functions */
73 /* 64 bits PSCI default functions */
100 /* PSCI call is Fast Call(atomic), so mask DAIF */
102 stp x15, xzr, [sp, #-16]!
106 stp x29, x30, [sp, #-16]!
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H A Dfwcall.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
12 #include <asm/psci.h>
25 "ldr x1, %1\n" in hvc_call()
34 "str x1, %1\n" in hvc_call()
37 : "+m" (args->regs[0]), "+m" (args->regs[1]), in hvc_call()
38 "+m" (args->regs[2]), "+m" (args->regs[3]) in hvc_call()
39 : "m" (args->regs[4]), "m" (args->regs[5]), in hvc_call()
40 "m" (args->regs[6]), "m" (args->regs[7]) in hvc_call()
59 "ldr x1, %1\n" in smc_call()
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/openbmc/qemu/target/arm/tcg/
H A Dpsci.c2 * Copyright (C) 2014 - Linaro
21 #include "exec/helper-proto.h"
22 #include "kvm-consts.h"
23 #include "qemu/main-loop.h"
26 #include "arm-powerctl.h"
32 * Return true if the exception type matches the configured PSCI conduit. in arm_is_psci_call()
34 * whether we should treat it as a PSCI call or with the architecturally in arm_is_psci_call()
41 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) { in arm_is_psci_call()
46 if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { in arm_is_psci_call()
61 * Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b), in arm_handle_psci_call()
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/openbmc/qemu/hw/arm/
H A Dboot.c4 * Copyright (c) 2006-2007 CodeSourcery.
12 #include "qemu/error-report.h"
16 #include "hw/arm/linux-boot-if.h"
30 #include "qemu/config-file.h"
59 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { in arm_boot_address_space()
69 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
73 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
75 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */
76 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */
77 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */
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/openbmc/u-boot/arch/arm/include/asm/
H A Dpsci.h2 * Copyright (C) 2013 - ARM Ltd
24 /* PSCI 0.1 interface */
29 #define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1)
34 #define ARM_PSCI_RET_NI (-1)
35 #define ARM_PSCI_RET_INVAL (-2)
36 #define ARM_PSCI_RET_DENIED (-3)
37 #define ARM_PSCI_RET_ALREADY_ON (-4)
38 #define ARM_PSCI_RET_ON_PENDING (-5)
39 #define ARM_PSCI_RET_INTERNAL_FAILURE (-6)
40 #define ARM_PSCI_RET_NOT_PRESENT (-7)
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/openbmc/qemu/target/arm/
H A Dkvm-consts.h8 * KVM headers. If CONFIG_KVM is set, we do a compile-time check
12 * See the COPYING file in the top-level directory.
20 #include <linux/psci.h>
46 #define QEMU_PSCI_0_1_FN_CPU_OFF QEMU_PSCI_0_1_FN(1)
64 #define QEMU_PSCI_0_2_FN_CPU_SUSPEND QEMU_PSCI_0_2_FN(1)
74 #define QEMU_PSCI_0_2_FN64_CPU_SUSPEND QEMU_PSCI_0_2_FN64(1)
91 /* PSCI v0.2 return values used by TCG emulation of PSCI */
104 MISMATCH_CHECK(QEMU_PSCI_VERSION_1_1, PSCI_VERSION(1, 1));
106 /* PSCI return values (inclusive of all PSCI versions) */
108 #define QEMU_PSCI_RET_NOT_SUPPORTED -1
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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/
H A D0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch11 Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
12 Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30118/2]
13 ---
15 1 file changed, 9 insertions(+)
17 diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/com…
19 --- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
21 @@ -7,6 +7,7 @@
22 #include <lib/psci/psci.h>
28 * platform layer will take care of registering the handlers with PSCI.
29 @@ -18,6 +19,14 @@ static void __dead2 corstone1000_system_reset(void)
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/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dpsci.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/psci.h>
16 #include <asm/psci.h>
20 #include "../soc-info.h"
21 #include "arm-mpcore.h"
22 #include "cache-uniphier.h"
40 return 1; in uniphier_get_nr_cpus()
55 if (nr_cpus == 1) in uniphier_smp_kick_all_cpus()
66 trmp_size = trmp_src_end - trmp_src; in uniphier_smp_kick_all_cpus()
68 trmp_dest = trmp_src & (SZ_64K - 1); in uniphier_smp_kick_all_cpus()
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