| /openbmc/linux/Documentation/devicetree/bindings/input/ |
| H A D | ti,drv260x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments - drv260x Haptics driver family
10 - Andrew Davis <afd@ti.com>
15 - ti,drv2604
16 - ti,drv2605
17 - ti,drv2605l
22 vbat-supply:
30 (defined in include/dt-bindings/input/ti-drv260x.h)
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| /openbmc/linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | richtek,rt5033-charger.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/richtek,rt5033-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jakob Hauser <jahau@rocketmail.com>
14 under sub-node named "charger" using the following format.
18 const: richtek,rt5033-charger
20 monitored-battery:
26 precharge-current-microamp:
27 Current of pre-charge mode. The pre-charge current levels are 350 mA
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| /openbmc/linux/Documentation/gpu/amdgpu/display/ |
| H A D | display-manager.rst | 8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
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| H A D | dcn-overview.rst | 10 .. kernel-figure:: dc_pipeline_overview.svg
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
24 multiple planes, using global or per-pixel alpha.
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43 the Display Micro-Controller Unit - version B (DMCUB), which is handled via
84 ----------------------
100 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
106 ---------
114 representation and convert them to a DCN specific floating-point format (i.e.,
115 different from the IEEE floating-point format). In the process, CNVC also
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | mtd.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 User-defined MTD device name. Can be used to assign user friendly
24 '#address-cells':
27 '#size-cells':
34 - compatible
37 "@[0-9a-f]+$":
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_wopcm.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2017-2019 Intel Corporation
26 * | Size +--------------------+
28 * | | +--------------------+
30 * | | +------------------- +
34 * | +------------------- + <== HuC Firmware Top
73 * intel_wopcm_init_early() - Early initialization of the WOPCM.
81 struct drm_i915_private *i915 = gt->i915; in intel_wopcm_init_early()
87 wopcm->size = GEN11_WOPCM_SIZE; in intel_wopcm_init_early()
89 wopcm->size = GEN9_WOPCM_SIZE; in intel_wopcm_init_early()
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| /openbmc/linux/drivers/mtd/chips/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
92 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
28 still be programmed into the chip and the driver will leave them "as is".
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
37 "silabs,si5344" - Si5344 A/B/C/D
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| /openbmc/linux/Documentation/trace/coresight/ |
| H A D | coresight-config.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 programming of the CoreSight system with pre-defined configurations that
17 Many CoreSight components can be programmed in complex ways - especially ETMs.
30 --------
41 accesses in the driver - the resource usage and parameter descriptions
43 and efficient for the feature to be programmed onto the device when required.
47 will be programmed into the device hardware.
56 feature being enabled that can adjust the behaviour of the operation programmed
59 For example, this could be a count value in a programmed operation that repeats
67 system - which is described below.
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| /openbmc/u-boot/include/ |
| H A D | spartan3.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
14 xilinx_pre_fn pre; member
31 xilinx_pre_fn pre; member
51 /* Spartan-III (1.2V) */
61 /* Spartan-3E (v3.4) */
69 * Spartan-6 : the Spartan-6 family can be programmed
70 * exactly as the Spartan-3
76 /* Spartan-III devices */
109 /* Spartan-3E devices */
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
36 #include <linux/clk-provider.h>
37 #include "clk-cpu.h"
101 pr_err("%s: re-parenting mux timed-out\n", __func__); in wait_until_mux_stable()
135 * dividers to be programmed.
148 /* handler for pre-rate change notification from parent clock */
152 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_pre_rate_change()
153 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos_cpuclk_pre_rate_change()
159 while ((cfg_data->prate * 1000) != ndata->new_rate) { in exynos_cpuclk_pre_rate_change()
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| /openbmc/u-boot/board/sunxi/ |
| H A D | README.nand | 4 A lot of Allwinner devices, especially the older ones (pre-H3 era),
21 SPL image that is ready to be programmed directly embedding the ECCs,
23 bitflips. The U-Boot build system, when configured for the NAND (with
24 CONFIG_NAND=y) will also generate the image sunxi-spl-with-ecc.bin
27 In order to flash your U-Boot image onto a board, assuming that the
28 board is in FEL mode, you'll need the sunxi-tools that you can find at
29 this repository: https://github.com/linux-sunxi/sunxi-tools
32 sunxi-fel spl spl/sunxi-spl.bin
35 sunxi-fel write 0x4a000000 u-boot-dtb.bin
36 sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | fsl_lbc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright © 2007-2008 MontaVista Software, Inc.
10 * Author: Roy Zang <tie-fei.zang@freescale.com>
36 * fsl_lbc_addr - convert the base address
46 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node; in fsl_lbc_addr()
57 * fsl_lbc_find - find Localbus bank
70 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) in fsl_lbc_find()
71 return -ENODEV; in fsl_lbc_find()
73 lbc = fsl_lbc_ctrl_dev->regs; in fsl_lbc_find()
74 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) { in fsl_lbc_find()
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| /openbmc/u-boot/drivers/clk/sifive/ |
| H A D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
27 * pre-determined set of performance points.
30 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
31 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
39 #include "analogbits-wrpll-cln28hpc.h"
47 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
50 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
79 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
83 * on the input clock frequency after the post-R-divider @post_divr_freq.
88 * or -1 upon error.
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| /openbmc/linux/drivers/clk/analogbits/ |
| H A D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
43 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
72 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
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| /openbmc/linux/Documentation/leds/ |
| H A D | leds-lm3556.rst | 6 1.5 A Synchronous Boost LED Flash Driver w/ High-Side Current Source
10 - Daniel Jeong
12 Contact:Daniel Jeong(daniel.jeong-at-ti.com, gshark.jeong-at-gmail.com)
15 -----------
50 In Torch Mode, the current source(LED) is programmed via the CURRENT CONTROL
78 and 4 patterns are pre-defined in indicator_pattern array.
80 According to N-lank, Pulse time and N Period values, different pattern wiill
84 Please refer datasheet for more detail about N-Blank, Pulse time and N Period.
118 -----
121 according to include/linux/platform_data/leds-lm3556.h, set the i2c board info
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| /openbmc/linux/drivers/power/supply/ |
| H A D | smb347-charger.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <dt-bindings/power/summit,smb347-charger.h>
26 #define SMB3XX_SOFT_TEMP_COMPENSATE_DEFAULT -1
28 /* Use default factory programmed value for hard/soft temperature limit */
29 #define SMB3XX_TEMP_USE_DEFAULT -273
34 * reloaded from non-volatile registers after POR.
136 * struct smb347_charger - smb347 charger instance
149 * @pre_charge_current: current (in uA) to use in pre-charging phase
153 * pre-charge to fast charge mode
158 * current [%100 - %130] (in degree C)
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| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | qcom,spmi-vadc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
86 * @returns 0 if ok, -1 on error (invalid clock id)
143 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
145 * @param reset 1 to assert reset, 0 to de-assert
154 * Warning: This function is only for use pre-relocation. Please use
168 * @param source source clock (0-15 depending on mux_bits)
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| /openbmc/linux/Documentation/devicetree/bindings/display/mediatek/ |
| H A D | mediatek,ethdr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
21 These two function blocks read the pre-programmed registers from DRAM and
22 set them to HW in the v-blanking period.
26 const: mediatek,mt8195-disp-ethdr
31 reg-names:
33 - const: mixer
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| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | ext-ctrls-flash.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _flash-controls:
17 .. _flash-controls-use-cases:
24 ------------------------------------------
35 ----------------------------------------
37 The synchronised LED flash is pre-programmed by the host (power and
46 ------------------
52 .. _flash-control-id:
55 -----------------
61 Defines the mode of the flash LED, the high-power white LED attached
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| /openbmc/linux/sound/oss/dmasound/ |
| H A D | dmasound_atari.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 * - added versioning
12 * - put in and populated the hardware_afmts field.
13 * [0.2] - put in SNDCTL_DSP_GETCAPS value.
14 * 01/02/2001 [0.3] - put in default hard/soft settings.
171 return -EFAULT; in ata_ct_law()
173 count--; in ata_ct_law()
192 return -EFAULT; in ata_ct_s8()
211 return -EFAULT; in ata_ct_u8()
213 count--; in ata_ct_u8()
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | maxim,max9286.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jacopo Mondi <jacopo+renesas@jmondi.org>
12 - Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
13 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 - Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
18 Serial Links (GMSL) and outputs them on a CSI-2 D-PHY port using up to 4 data
28 '#address-cells':
31 '#size-cells':
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| /openbmc/u-boot/arch/arm/mach-kirkwood/ |
| H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
21 writel(readl(&cpureg->rstoutn_mask) | (1 << 2), in reset_cpu()
22 &cpureg->rstoutn_mask); in reset_cpu()
23 writel(readl(&cpureg->sys_soft_rst) | 1, in reset_cpu()
24 &cpureg->sys_soft_rst); in reset_cpu()
31 * Must be programmed from LSB to MSB as sequence of ones followed by
34 * NOTE: A value of 0x0 specifies 64-KByte size.
50 * kw_config_adr_windows - Configure address Windows
59 * Mbus-L to Mbus Bridge Registers Configuration.
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| /openbmc/linux/Documentation/power/ |
| H A D | pci.rst | 13 power management refer to Documentation/driver-api/pm/devices.rst and
27 1.1. Native and Platform-Based Power Management
28 -----------------------------------------------
31 devices into states in which they draw less power (low-power states) at the
34 Usually, a device is put into a low-power state when it is underutilized or
36 again, it has to be put back into the "fully functional" state (full-power
41 PCI devices may be put into low-power states in two ways, by using the device
53 to put the device that sent it into the full-power state. However, the PCI Bus
68 Thus in many situations both the native and the platform-based power management
72 --------------------------------
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