asm/arch-tegra/clock.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
29  * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
71  * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77  * Read low-level parameters of a PLL.
86  * @returns 0 if ok, -1 on error (invalid clock id)
143  * @param cpu		cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
145  * @param reset		1 to assert reset, 0 to de-assert
154  * Warning: This function is only for use pre-relocation. Please use
168  * @param source	source clock (0-15 depending on mux_bits)
178  * Warning: This function is only for use pre-relocation. Please use
191  * specific knowledge of system-level clock tree structure.
205  * @return rate selected in Hz, or -1U if something went wrong
232  * @param extra_div	value for the second-stage divisor (NULL if one is
234  * @return rate selected in Hz, or -1U if something went wrong
248  * Start up a UART using low-level calls
251  * function provides a way to set up a UART using low-level calls which
280  * @return 0 if ok, -1 on error
301  * clock's register, the number of divider bits the clock has, and the SoC-
304  * This is an internal API between the core Tegra clock code and the SoC-
310  * @param type          Set to the SoC-specific clock type
311  * @return 0 on success, -1 on error
320  * This is an internal API between the core Tegra clock code and the SoC-
331  * value should be programmed into the source mux for that peripheral.
339  * @return mux value (0-4, or -1 if not found)
356  * PLL output frequencies are programmed by setting their N, M and P values.
368  * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
381 /* SoC-specific TSC init */
386 /* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
387 #define CLOCK_ID_PLL_COUNT	(CLOCK_ID_COUNT - 3)
417  * @return 0 if OK. -ve on error