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/openbmc/qemu/hw/net/rocker/
H A Drocker_fp.c44 char *fp_port_get_name(FpPort *port) in fp_port_get_name() argument
46 return port->name; in fp_port_get_name()
49 bool fp_port_get_link_up(FpPort *port) in fp_port_get_link_up() argument
51 return !qemu_get_queue(port->nic)->link_down; in fp_port_get_link_up()
54 RockerPort *fp_port_get_info(FpPort *port) in fp_port_get_info() argument
58 value->name = g_strdup(port->name); in fp_port_get_info()
59 value->enabled = port->enabled; in fp_port_get_info()
60 value->link_up = fp_port_get_link_up(port); in fp_port_get_info()
61 value->speed = port->speed; in fp_port_get_info()
62 value->duplex = port->duplex; in fp_port_get_info()
[all …]
H A Drocker_fp.h27 int fp_port_eg(FpPort *port, const struct iovec *iov, int iovcnt);
29 char *fp_port_get_name(FpPort *port);
30 bool fp_port_get_link_up(FpPort *port);
31 RockerPort *fp_port_get_info(FpPort *port);
32 void fp_port_get_macaddr(FpPort *port, MACAddr *macaddr);
33 void fp_port_set_macaddr(FpPort *port, MACAddr *macaddr);
34 uint8_t fp_port_get_learning(FpPort *port);
35 void fp_port_set_learning(FpPort *port, uint8_t learning);
36 int fp_port_get_settings(FpPort *port, uint32_t *speed,
38 int fp_port_set_settings(FpPort *port, uint32_t speed,
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmsg_port.h38 * msg_port_setup - set up the message port control register
41 * @port: port number on the message bus
42 * @reg: register number within a port
44 void msg_port_setup(int op, int port, int reg);
47 * msg_port_read - read a message port register using normal opcode
49 * @port: port number on the message bus
50 * @reg: register number within a port
52 * @return: message port register value
54 u32 msg_port_read(u8 port, u32 reg);
57 * msg_port_write - write a message port register using normal opcode
[all …]
/openbmc/qemu/hw/char/
H A Dvirtio-serial-bus.c41 VirtIOSerialPort *port; in find_port_by_id() local
47 QTAILQ_FOREACH(port, &vser->ports, next) { in find_port_by_id()
48 if (port->id == id) in find_port_by_id()
49 return port; in find_port_by_id()
56 VirtIOSerialPort *port; in find_port_by_vq() local
58 QTAILQ_FOREACH(port, &vser->ports, next) { in find_port_by_vq()
59 if (port->ivq == vq || port->ovq == vq) in find_port_by_vq()
60 return port; in find_port_by_vq()
70 VirtIOSerialPort *port; in find_port_by_name() local
72 QTAILQ_FOREACH(port, &vser->ports, next) { in find_port_by_name()
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_sh.c26 static int scif_rxfill(struct uart_port *port) in scif_rxfill() argument
28 return sci_in(port, SCRFDR) & 0xff; in scif_rxfill()
31 static int scif_rxfill(struct uart_port *port) in scif_rxfill() argument
33 if ((port->mapbase == 0xffe00000) || in scif_rxfill()
34 (port->mapbase == 0xffe08000)) { in scif_rxfill()
36 return sci_in(port, SCRFDR) & 0xff; in scif_rxfill()
39 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; in scif_rxfill()
43 static int scif_rxfill(struct uart_port *port) in scif_rxfill() argument
45 if (port->type == PORT_SCIFA) in scif_rxfill()
46 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; in scif_rxfill()
[all …]
H A Dserial_ns16550.c27 #error "Console port 1 defined but not configured."
29 #error "Console port 2 defined but not configured."
31 #error "Console port 3 defined but not configured."
33 #error "Console port 4 defined but not configured."
35 #error "Console port 5 defined but not configured."
37 #error "Console port 6 defined but not configured."
40 /* Note: The port number specified in the functions is 1 based.
76 #define PORT serial_ports[port-1] macro
79 #define DECLARE_ESERIAL_FUNCTIONS(port) \ argument
80 static int eserial##port##_init(void) \
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/openbmc/u-boot/drivers/misc/
H A Dsmsc_sio1007.c11 static inline u8 sio1007_read(int port, int reg) in sio1007_read() argument
13 outb(reg, port); in sio1007_read()
15 return inb(port + 1); in sio1007_read()
18 static inline void sio1007_write(int port, int reg, int val) in sio1007_write() argument
20 outb(reg, port); in sio1007_write()
21 outb(val, port + 1); in sio1007_write()
24 static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) in sio1007_clrsetbits() argument
26 sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set); in sio1007_clrsetbits()
29 void sio1007_enable_serial(int port, int num, int iobase, int irq) in sio1007_enable_serial() argument
35 outb(0x55, port); in sio1007_enable_serial()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xxx/
H A Dsrio.c53 * Description: During port initialization, the SRIO port performs
58 * the configured port width.
59 * An SRIO port configured as a 4x port may see one of these scenarios:
65 * An SRIO port configured as a 1x port may fail to complete port
67 * Impact: SRIO port may downtrain to 1x, or may fail to complete
68 * link initialization. Once a port completes link initialization
71 static int srio_erratum_a004034(u8 port) in srio_erratum_a004034() argument
83 >> (12 - port * 4)) & 0x3; in srio_erratum_a004034()
85 .port[port].pccsr) >> 27) & 0x7; in srio_erratum_a004034()
90 * corresponding to the SERDES bank/PLL for the SRIO port). in srio_erratum_a004034()
[all …]
/openbmc/u-boot/include/
H A Dsh_pfc.h117 /* helper macro for port */
135 #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
136 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
144 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
147 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
148 PORT##nr##_IN, PORT##nr##_IN_PD)
151 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
152 PORT##nr##_IN, PORT##nr##_IN_PU)
155 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
156 PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c209 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; in imx_gpio_mode() local
217 writel(readl(&regs->port[port].puen) | (1 << pin), in imx_gpio_mode()
218 &regs->port[port].puen); in imx_gpio_mode()
220 writel(readl(&regs->port[port].puen) & ~(1 << pin), in imx_gpio_mode()
221 &regs->port[port].puen); in imx_gpio_mode()
226 writel(readl(&regs->port[port].gpio_dir) | 1 << pin, in imx_gpio_mode()
227 &regs->port[port].gpio_dir); in imx_gpio_mode()
229 writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin), in imx_gpio_mode()
230 &regs->port[port].gpio_dir); in imx_gpio_mode()
235 writel(readl(&regs->port[port].gpr) | (1 << pin), in imx_gpio_mode()
[all …]
/openbmc/u-boot/drivers/ata/
H A Dsata_sil3114.c39 static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE]; variable
60 port[num].dev_mask = 1; in sata_bus_softreset()
62 port[num].ctl_reg = 0x08; /*Default value of control reg */ in sata_bus_softreset()
63 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
65 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
67 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
78 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0); in sata_bus_softreset()
81 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0); in sata_bus_softreset()
90 status = sata_chk_status (&port[num].ioaddr, 0); in sata_bus_softreset()
96 port[num].dev_mask = 0; in sata_bus_softreset()
[all …]
/openbmc/qemu/net/
H A Dhub.c26 * A hub broadcasts incoming packets to all its ports except the source port.
51 NetHubPort *port; in net_hub_receive() local
53 QLIST_FOREACH(port, &hub->ports, next) { in net_hub_receive()
54 if (port == source_port) { in net_hub_receive()
58 qemu_send_packet(&port->nc, buf, len); in net_hub_receive()
66 NetHubPort *port; in net_hub_receive_iov() local
69 QLIST_FOREACH(port, &hub->ports, next) { in net_hub_receive_iov()
70 if (port == source_port) { in net_hub_receive_iov()
74 qemu_sendv_packet(&port->nc, iov, iovcnt); in net_hub_receive_iov()
95 NetHubPort *port; in net_hub_port_can_receive() local
[all …]
/openbmc/u-boot/drivers/net/
H A Dmvpp2.c68 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
69 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
74 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
95 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
96 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
97 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) argument
98 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) argument
99 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
100 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) argument
101 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) argument
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_5445x.h101 u8 podr_fec0h; /* FEC0 High Port Output Data Register */
102 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
103 u8 podr_ssi; /* SSI Port Output Data Register */
104 u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
105 u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
106 u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
107 u8 podr_dma; /* DMA Port Output Data Register */
108 u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
110 u8 podr_uart; /* UART Port Output Data Register */
111 u8 podr_dspi; /* DSPI Port Output Data Register */
[all …]
H A Dio.h46 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) argument
47 #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) argument
48 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) argument
49 #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) argument
50 #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) argument
51 #define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) argument
53 #define inb(port) in_8((u8 *)((port)+_IO_BASE)) argument
54 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) argument
56 #define inw(port) in_be16((u16 *)((port)+_IO_BASE)) argument
57 #define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) argument
[all …]
/openbmc/u-boot/doc/
H A DREADME.t1040-l2switch6 VSC9953 is an 8-port Gigabit Ethernet switch supports the following features:
17 - RMON counters per port
27 - enable/disable a port or show its configuration (speed, duplexity, status, etc.)
28 - port statistics
31 - Port-based VLAN
34 - Port LAG
37 ethsw [port <port_no>] { enable | disable | show } - enable/disable a port; show a port's configura…
38 ethsw [port <port_no>] statistics { [help] | [clear] } - show an l2 switch port's statistics
39 ethsw [port <port_no>] learning { [help] | show | auto | disable } - enable/disable/show learning c…
40 ethsw [port <port_no>] [vlan <vid>] fdb { [help] | show | flush | { add | del } <mac> } - add/delet…
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/openbmc/bmcweb/redfish-core/schema/dmtf/installed/
H A DPort_v1.xml4 <!--# Redfish Schema: Port v1.16.0 -->
64 <Schema xmlns="http://docs.oasis-open.org/odata/ns/edm" Namespace="Port">
68 <EntityType Name="Port" BaseType="Resource.v1_0_0.Resource" Abstract="true">
69 …<Annotation Term="OData.Description" String="The `Port` schema contains properties that describe a…
70 …<Annotation Term="OData.LongDescription" String="This resource contains a simple port for a Redfis…
125 <Annotation Term="OData.Description" String="This action resets this port."/>
126 <Annotation Term="OData.LongDescription" String="This action shall reset this port."/>
127 <Parameter Name="Port" Type="Port.v1_0_0.Actions"/>
135 …n Term="OData.Description" String="This action resets the PCI-to-PCI bridge (PPB) for this port."/>
136 …Data.LongDescription" String="This action shall reset the PCI-to-PCI bridge (PPB) for this port."/>
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DPort_v1.xml4 <!--# Redfish Schema: Port v1.16.0 -->
64 <Schema xmlns="http://docs.oasis-open.org/odata/ns/edm" Namespace="Port">
68 <EntityType Name="Port" BaseType="Resource.v1_0_0.Resource" Abstract="true">
69 …<Annotation Term="OData.Description" String="The `Port` schema contains properties that describe a…
70 …<Annotation Term="OData.LongDescription" String="This resource contains a simple port for a Redfis…
125 <Annotation Term="OData.Description" String="This action resets this port."/>
126 <Annotation Term="OData.LongDescription" String="This action shall reset this port."/>
127 <Parameter Name="Port" Type="Port.v1_0_0.Actions"/>
135 …n Term="OData.Description" String="This action resets the PCI-to-PCI bridge (PPB) for this port."/>
136 …Data.LongDescription" String="This action shall reset the PCI-to-PCI bridge (PPB) for this port."/>
[all …]
/openbmc/qemu/hw/usb/
H A Ddev-hub.c40 USBPort port; member
162 0x00, /* (per-port OC, no power switching) */
169 static bool usb_hub_port_change(USBHubPort *port, uint16_t status) in usb_hub_port_change() argument
174 port->wPortChange |= status; in usb_hub_port_change()
180 static bool usb_hub_port_set(USBHubPort *port, uint16_t status) in usb_hub_port_set() argument
182 if (port->wPortStatus & status) { in usb_hub_port_set()
185 port->wPortStatus |= status; in usb_hub_port_set()
186 return usb_hub_port_change(port, status); in usb_hub_port_set()
189 static bool usb_hub_port_clear(USBHubPort *port, uint16_t status) in usb_hub_port_clear() argument
191 if (!(port->wPortStatus & status)) { in usb_hub_port_clear()
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DNetworkPort.v1_4_3.json43 "None": "No IEEE 802.3x flow control is enabled on this port.",
57 "Ethernet": "The port is capable of connecting to an Ethernet network.",
58 "FibreChannel": "The port is capable of connecting to a Fibre Channel network.",
59 "InfiniBand": "The port is capable of connecting to an InfiniBand network."
71 "Down": "The port is enabled but link is down.",
72 …his interface is starting. A physical link has been established, but the port is not able to tran…
74 "Up": "The port is enabled and link is good (up)."
84 …"A maximum bandwidth allocation percentage for a network device functions associated with a port.",
85 …e a maximum bandwidth percentage allocation for a network device function associated with a port.",
113 … link to the network device function associated with this bandwidth setting of this network port.",
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dio.h43 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) argument
44 #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) argument
45 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) argument
46 #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) argument
47 #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) argument
48 #define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) argument
50 #define inb(port) in_8((u8 *)((port)+_IO_BASE)) argument
51 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) argument
53 #define inw(port) in_be16((u16 *)((port)+_IO_BASE)) argument
54 #define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) argument
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dboard_env_spec.h130 #define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000) argument
132 #define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804) argument
133 #define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C) argument
134 #define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918) argument
135 #define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) + 0x920) argument
136 #define SATA_LP_PHY_EXT_CTRL_REG(port) (SATA_BASE_REG(port) + 0x058) argument
137 #define SATA_LP_PHY_EXT_STAT_REG(port) (SATA_BASE_REG(port) + 0x05C) argument
138 #define SATA_IMP_TX_SSC_CTRL_REG(port) (SATA_BASE_REG(port) + 0x810) argument
139 #define SATA_GEN_1_SET_0_REG(port) (SATA_BASE_REG(port) + 0x834) argument
140 #define SATA_GEN_1_SET_1_REG(port) (SATA_BASE_REG(port) + 0x838) argument
[all …]
/openbmc/openbmc-test-automation/lib/snmp/
H A Dsnmp_utils.robot24 [Arguments] ${snmp_ip} ${port} ${expected_result}
28 # port Network port where SNMP manager is listening.
31 @{snmp_parm_list}= Create List ${snmp_ip} ${port}
46 Get List Of SNMP Manager And Port Configured On BMC
58 # "Port": 186
63 ${port}= Read Attribute ${snmp_uri} Port
64 Append To List ${ip_and_port_list} ${ip} ${port}
72 [Arguments] ${snmp_ip} ${port}
76 # port Network port where SNMP manager is listening.
78 @{ip_and_port}= Create List ${snmp_ip} ${port}
[all …]
/openbmc/u-boot/arch/xtensa/include/asm/
H A Dio.h59 #define inb(port) readb((u8 *)((port))) argument
60 #define outb(val, port) writeb((val), (u8 *)((unsigned long)(port))) argument
61 #define inw(port) readw((u16 *)((port))) argument
62 #define outw(val, port) writew((val), (u16 *)((unsigned long)(port))) argument
63 #define inl(port) readl((u32 *)((port))) argument
64 #define outl(val, port) writel((val), (u32 *)((unsigned long)(port))) argument
66 #define inb_p(port) inb((port)) argument
67 #define outb_p(val, port) outb((val), (port)) argument
68 #define inw_p(port) inw((port)) argument
69 #define outw_p(val, port) outw((val), (port)) argument
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DPort.v1_16_0.json2 "$id": "http://redfish.dmtf.org/schemas/v1/Port.v1_16_0.json",
3 "$ref": "#/definitions/Port",
26 "#Port.Reset": {
29 "#Port.ResetPPB": {
42 "description": "CXL properties for a port.",
43 "longDescription": "This type shall contain CXL-specific properties for a port.",
68 "description": "The congestion properties for this CXL port.",
69 … "longDescription": "This property shall contain the congestion properties for this CXL port.",
109 "description": "The current port configuration state.",
110 …ion": "This property shall contain the CXL Specification-defined 'Current Port Configuration State…
[all …]

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