Searched full:pmux (Results 1 – 15 of 15) sorted by relevance
89 u32 pmux; in portmux_setup() local93 pmux = gpio_array[gpio_bank(ident)]->port_mux; in portmux_setup()95 pmux &= ~(0x3 << (2 * gpio_sub_n(ident))); in portmux_setup()96 pmux |= (function & 0x3) << (2 * gpio_sub_n(ident)); in portmux_setup()98 gpio_array[gpio_bank(ident)]->port_mux = pmux; in portmux_setup()103 u32 pmux; in get_portmux() local106 pmux = gpio_array[gpio_bank(ident)]->port_mux; in get_portmux()108 return pmux >> (2 * gpio_sub_n(ident)) & 0x3; in get_portmux()
428 sd1_pmux: sd1-pmux {433 twsi0_pmux: twsi0-pmux {438 twsi1_pmux: twsi1-pmux {628 uart0_pmux: uart0-pmux {633 uart1_pmux: uart1-pmux {638 twsi2_pmux: twsi2-pmux {643 twsi3_pmux: twsi3-pmux {
391 emmc_pmux: emmc-pmux {514 uart0_pmux: uart0-pmux {519 uart1_pmux: uart1-pmux {523 uart2_pmux: uart2-pmux {
73 ledpwm_pmux: ledpwm-pmux {
82 sd1gpio_pmux: sd1pwr-pmux {
396 uart0_pmux: uart0-pmux {
58 pmux: mux-controller@50 {72 mux-controls = <&pmux>;
26 * | +------+-----------+ +------>2 PMUX |46 * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk48 * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk559 * chaging the parent of PMUX. This can result in pmux getting in cpu_clk_notifier_cb()
190 * chaging the parent of PMUX. This can result in pmux getting in cbf_clk_notifier_cb()
38 uart0_pmux: uart0-pmux {
87 pmux: pinmux@24190000 {
62 gpio-ranges = <&pmux 0 0 32>;
3 &pmux {
163 pmux: pmux@24190000 { label172 gpio-ranges = <&pmux 0 0 32>;
310 uart0_pmux: uart0-pmux {