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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun6i-a31-pll6-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml#
23 const: allwinner,sun6i-a31-pll6-clk
47 compatible = "allwinner,sun6i-a31-pll6-clk";
50 clock-output-names = "pll6", "pll6x2";
H A Dallwinner,sun4i-a10-pll6-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
23 const: allwinner,sun4i-a10-pll6-clk
47 compatible = "allwinner,sun4i-a10-pll6-clk";
50 clock-output-names = "pll6_sata", "pll6_other", "pll6";
H A Dallwinner,sun4i-a10-mbus-clk.yaml50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
H A Dallwinner,sun4i-a10-usb-clk.yaml116 clocks = <&pll6 1>;
126 clocks = <&pll6 1>;
H A Dallwinner,sun5i-a13-ahb-clk.yaml48 clocks = <&axi>, <&cpu>, <&pll6 1>;
H A Dallwinner,sun4i-a10-apb1-clk.yaml48 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
H A Dallwinner,sun4i-a10-mmc-clk.yaml71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mod0-clk.yaml67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-ahb-clk.yaml95 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun6i.h24 u32 pll6_cfg; /* 0x28 pll6 control */
135 u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
149 u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
273 #define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
275 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
384 #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
448 #define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
450 #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
H A Dclock_sun8i_a83t.h27 u32 pll6_cfg; /* 0x28 pll6 peripheral control */
100 u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */
245 #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
266 #define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */
H A Dclock_sun4i.h24 u32 pll6_cfg; /* 0x28 pll6 control */
25 u32 pll6_tun; /* 0x2c pll6 tuning */
148 * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
H A Dclock_sun50i_h6.h17 u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
61 u32 pll6_bias; /* 0x320 pll6 (periph0) bias */
241 /* pll6 bit field */
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun50i_h6.c92 /* The register defines PLL6-4X, not plain PLL6 */ in clock_get_pll6()
H A Ddram_sun9i.c51 * 3) The controller supports two different clocking strategies (PLL6 can
205 debug("Setting PLL6 to %d\n", DRAM_CLK * 2); in mctl_sys_init()
214 * PLL6 should be 2*CK * in mctl_sys_init()
218 * PLL6 should be CK/2 * in mctl_sys_init()
301 writel(2, &mctl_com->rmcr); /* controller clock is PLL6/4 */ in mctl_sys_init()
308 * PLL6 should be 2*CK * in mctl_sys_init()
313 mctl_write_w(MC_RMCR, 0x2); * controller clock use pll6/4 * in mctl_sys_init()
319 mctl_write_w(MC_RMCR, 0x0); * controller clock use pll6 * in mctl_sys_init()
H A Ddram_sun4i.c305 /* PLL5P and PLL6 are the potential clock sources for MBUS */ in mctl_setup_dram_clock()
308 pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ in mctl_setup_dram_clock()
317 /* use PLL6 as the MBUS clock source */ in mctl_setup_dram_clock()
H A Dclock_sun8i_a83t.c36 /* switch before changing pll6 */ in clock_init_safe()
/openbmc/linux/drivers/clk/renesas/
H A Dr8a779f0-cpg-mssr.c65 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
191 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
H A Dr8a779g0-cpg-mssr.c75 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
247 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
259 …/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div O…
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c259 * can work at speeds up to 300M, just after reparenting to pll6 in sun5i_a13_get_ahb_factors()
284 * if parent is pll6, then
285 * parent_rate = pll6 rate / (m + 1)
301 /* calculate pre-divider if parent is pll6 */ in sun6i_get_ahb1_factors()
331 /* apply pre-divider first if parent is pll6 */ in sun6i_ahb1_recalc()
919 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1121 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1128 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dallwinner,sun4i-a10-ahci.yaml45 clocks = <&pll6 0>, <&ahb_gates 25>;
/openbmc/qemu/hw/misc/
H A Dallwinner-a10-ccm.c41 REG_PLL6_CFG = 0x0028, /* PLL6 Control */
42 REG_PLL6_TUN = 0x002C, /* PLL6 Tuning */
/openbmc/linux/drivers/clk/
H A Dclk-milbeaut.c23 #define M10V_PLL6 "pll6"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,gcc-msm8660.h259 #define PLL6 250 macro
H A Dqcom,gcc-mdm9615.h293 #define PLL6 283 macro

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