1f95cad74SMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2f95cad74SMaxime Ripard%YAML 1.2 3f95cad74SMaxime Ripard--- 4f95cad74SMaxime Ripard$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml# 5f95cad74SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6f95cad74SMaxime Ripard 7*dd3cb467SAndrew Lunntitle: Allwinner A10 Module 1 Clock 8f95cad74SMaxime Ripard 9f95cad74SMaxime Ripardmaintainers: 10f95cad74SMaxime Ripard - Chen-Yu Tsai <wens@csie.org> 11f95cad74SMaxime Ripard - Maxime Ripard <mripard@kernel.org> 12f95cad74SMaxime Ripard 13f95cad74SMaxime Riparddeprecated: true 14f95cad74SMaxime Ripard 15f95cad74SMaxime Ripardproperties: 16f95cad74SMaxime Ripard "#clock-cells": 17f95cad74SMaxime Ripard const: 1 18f95cad74SMaxime Ripard description: > 19f95cad74SMaxime Ripard There is three different outputs: the main clock, with the ID 0, 20f95cad74SMaxime Ripard and the output and sample clocks, with the IDs 1 and 2, 21f95cad74SMaxime Ripard respectively. 22f95cad74SMaxime Ripard 23f95cad74SMaxime Ripard compatible: 24f95cad74SMaxime Ripard enum: 25f95cad74SMaxime Ripard - allwinner,sun4i-a10-mmc-clk 26f95cad74SMaxime Ripard - allwinner,sun9i-a80-mmc-clk 27f95cad74SMaxime Ripard 28f95cad74SMaxime Ripard reg: 29f95cad74SMaxime Ripard maxItems: 1 30f95cad74SMaxime Ripard 31f95cad74SMaxime Ripard clocks: 32f95cad74SMaxime Ripard minItems: 2 33f95cad74SMaxime Ripard maxItems: 3 34f95cad74SMaxime Ripard description: > 35f95cad74SMaxime Ripard The parent order must match the hardware programming order. 36f95cad74SMaxime Ripard 37f95cad74SMaxime Ripard clock-output-names: 38f95cad74SMaxime Ripard maxItems: 3 39f95cad74SMaxime Ripard 40f95cad74SMaxime Ripardrequired: 41f95cad74SMaxime Ripard - "#clock-cells" 42f95cad74SMaxime Ripard - compatible 43f95cad74SMaxime Ripard - reg 44f95cad74SMaxime Ripard - clocks 45f95cad74SMaxime Ripard - clock-output-names 46f95cad74SMaxime Ripard 47f95cad74SMaxime RipardadditionalProperties: false 48f95cad74SMaxime Ripard 49f95cad74SMaxime Ripardif: 50f95cad74SMaxime Ripard properties: 51f95cad74SMaxime Ripard compatible: 52f95cad74SMaxime Ripard contains: 53f95cad74SMaxime Ripard const: allwinner,sun4i-a10-mmc-clk 54f95cad74SMaxime Ripard 55f95cad74SMaxime Ripardthen: 56f95cad74SMaxime Ripard properties: 57f95cad74SMaxime Ripard clocks: 58f95cad74SMaxime Ripard maxItems: 3 59f95cad74SMaxime Ripard 60f95cad74SMaxime Ripardelse: 61f95cad74SMaxime Ripard properties: 62f95cad74SMaxime Ripard clocks: 63f95cad74SMaxime Ripard maxItems: 2 64f95cad74SMaxime Ripard 65f95cad74SMaxime Ripardexamples: 66f95cad74SMaxime Ripard - | 67f95cad74SMaxime Ripard clk@1c20088 { 68f95cad74SMaxime Ripard #clock-cells = <1>; 69f95cad74SMaxime Ripard compatible = "allwinner,sun4i-a10-mmc-clk"; 70f95cad74SMaxime Ripard reg = <0x01c20088 0x4>; 71f95cad74SMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 72f95cad74SMaxime Ripard clock-output-names = "mmc0", 73f95cad74SMaxime Ripard "mmc0_output", 74f95cad74SMaxime Ripard "mmc0_sample"; 75f95cad74SMaxime Ripard }; 76f95cad74SMaxime Ripard 77f95cad74SMaxime Ripard - | 78f95cad74SMaxime Ripard clk@6000410 { 79f95cad74SMaxime Ripard #clock-cells = <1>; 80f95cad74SMaxime Ripard compatible = "allwinner,sun9i-a80-mmc-clk"; 81f95cad74SMaxime Ripard reg = <0x06000410 0x4>; 82f95cad74SMaxime Ripard clocks = <&osc24M>, <&pll4>; 83f95cad74SMaxime Ripard clock-output-names = "mmc0", "mmc0_output", 84f95cad74SMaxime Ripard "mmc0_sample"; 85f95cad74SMaxime Ripard }; 86f95cad74SMaxime Ripard 87f95cad74SMaxime Ripard... 88