/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | nvidia,tegra124-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 20 - description: NVIDIA Tegra124 21 const: nvidia,tegra124-xusb 23 - description: NVIDIA Tegra132 25 - const: nvidia,tegra132-xusb [all …]
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H A D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 const: nvidia,tegra210-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers 24 - description: base and length of the XUSB IPFS registers [all …]
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H A D | nvidia,tegra194-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 const: nvidia,tegra194-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers 25 reg-names: [all …]
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H A D | nvidia,tegra186-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 const: nvidia,tegra186-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers 25 reg-names: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | pcm512x.txt | 8 - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or 11 - reg : the I2C address of the device for I2C, the chip select 14 - AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the 19 - clocks : A clock specifier for the clock connected as SCLK. If this 20 is absent the device will be configured to clock from BCLK. If pll-in 21 and pll-out are specified in addition to a clock, the device is 24 - pll-in, pll-out : gpio pins used to connect the pll using <1> 26 given pll-in pin and PLL output on the given pll-out pin. An 27 external connection from the pll-out pin to the SCLK pin is assumed. 35 AVDD-supply = <®_3v3_analog>; [all …]
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H A D | tas2552.txt | 1 Texas Instruments - tas2552 Codec module 6 - compatible - One of: 7 "ti,tas2552" - TAS2552 8 - reg - I2C slave address: it can be 0x40 if ADDR pin is 0 10 - supply-*: Required supply regulators are: 16 - enable-gpio - gpio pin to enable/disable the device 19 internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM 20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK. 21 For system integration the dt-bindings/sound/tas2552.h header file provides 22 defined values to select and configure the PLL and PDM reference clocks. [all …]
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H A D | adi,adau1701.txt | 5 - compatible: Should contain "adi,adau1701" 6 - reg: The i2c address. Value depends on the state of ADDR0 11 - reset-gpio: A GPIO spec to define which pin is connected to the 14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs 15 the ADAU's PLL config pins are connected to. 19 - adi,pin-config: An array of 12 numerical values selecting one of the 23 - avdd-supply: Power supply for AVDD, providing 3.3V 24 - dvdd-supply: Power supply for DVDD, providing 3.3V 32 reset-gpio = <&gpio 23 0>; 33 avdd-supply = <&vdd_3v3_reg>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sa8295p-adp.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 #include <dt-bindings/spmi/spmi.h> 14 #include "sa8540p-pmics.dtsi" 18 compatible = "qcom,sa8295p-adp", "qcom,sa8540p"; 25 stdout-path = "serial0:115200n8"; 28 dp2-connector { 29 compatible = "dp-connector"; [all …]
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H A D | sm8350-mtp.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 6 /dts-v1/; 8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 19 compatible = "qcom,sm8350-mtp", "qcom,sm8350"; 20 chassis-type = "handset"; 27 stdout-path = "serial0:115200n8"; 30 vph_pwr: vph-pwr-regulator { 31 compatible = "regulator-fixed"; 32 regulator-name = "vph_pwr"; 33 regulator-min-microvolt = <3700000>; [all …]
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H A D | sm8350-microsoft-surface-duo2.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 6 /dts-v1/; 8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 19 compatible = "microsoft,surface-duo2", "qcom,sm8350"; 20 chassis-type = "handset"; 27 stdout-path = "serial0:115200n8"; 30 vph_pwr: vph-pwr-regulator { 31 compatible = "regulator-fixed"; 32 regulator-name = "vph_pwr"; 33 regulator-min-microvolt = <3700000>; [all …]
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H A D | sm8150-hdk.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 6 /dts-v1/; 8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 9 #include <dt-bindings/gpio/gpio.h> 17 compatible = "qcom,sm8150-hdk", "qcom,sm8150"; 18 chassis-type = "embedded"; 25 stdout-path = "serial0:115200n8"; 28 vph_pwr: vph-pwr-regulator { 29 compatible = "regulator-fixed"; 30 regulator-name = "vph_pwr"; [all …]
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H A D | sc8280xp-crd.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 13 #include "sc8280xp-pmics.dtsi" 17 compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp"; 26 compatible = "pwm-backlight"; 28 enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; 29 power-supply = <&vreg_edp_bl>; 31 pinctrl-names = "default"; [all …]
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H A D | sm8350-hdk.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright (c) 2020-2021, Linaro Limited 6 /dts-v1/; 8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 14 compatible = "qcom,sm8350-hdk", "qcom,sm8350"; 15 chassis-type = "embedded"; 22 stdout-path = "serial0:115200n8"; 25 hdmi-connector { 26 compatible = "hdmi-connector"; 31 remote-endpoint = <<9611_out>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | qcom,msm8998-qmp-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-pcie-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vinod Koul <vkoul@kernel.org> 18 const: qcom,msm8998-qmp-pcie-phy 22 - description: serdes 27 clock-names: 29 - const: aux 30 - const: cfg_ahb [all …]
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H A D | qcom,qusb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Wesley Cheng <quic_wcheng@quicinc.com> 19 - items: 20 - enum: 21 - qcom,ipq6018-qusb2-phy 22 - qcom,ipq8074-qusb2-phy 23 - qcom,ipq9574-qusb2-phy [all …]
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/openbmc/u-boot/doc/device-tree-bindings/phy/ |
H A D | phy-stm32-usbphyc.txt | 6 PLL configuration. 9 |_ PLL 14 |_ PHY port#2 ----| |________________ 23 - compatible: must be "st,stm32mp1-usbphyc" 24 - reg: address and length of the usb phy control register set 25 - clocks: phandle + clock specifier for the PLL phy clock 26 - #address-cells: number of address cells for phys sub-nodes, must be <1> 27 - #size-cells: number of size cells for phys sub-nodes, must be <0> 30 - assigned-clocks: phandle + clock specifier for the PLL phy clock 31 - assigned-clock-parents: the PLL phy clock parent [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | ti,cdce925.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alexander Stein <alexander.stein@ew.tq-group.com> 15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913 16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925 17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937 18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949 23 - ti,cdce913 24 - ti,cdce925 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/ti/ |
H A D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 8 -------- 11 - compatible: "ti,omap4-dss" 12 - reg: address and length of the register space 13 - ti,hwmods: "dss_core" 14 - clocks: handle to fclk 15 - clock-names: "fck" 18 - DISPC 21 - DSS Submodules: RFBI, VENC, DSI, HDMI 22 - Video port for DPI output [all …]
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H A D | ti,omap5-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 8 -------- 11 - compatible: "ti,omap5-dss" 12 - reg: address and length of the register space 13 - ti,hwmods: "dss_core" 14 - clocks: handle to fclk 15 - clock-names: "fck" 18 - DISPC 21 - DSS Submodules: RFBI, DSI, HDMI 22 - Video port for DPI output [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra20-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^hdmi@[0-9a-f]+$" 19 - enum: 20 - nvidia,tegra20-hdmi 21 - nvidia,tegra30-hdmi [all …]
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H A D | nvidia,tegra124-sor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 19 pattern: "^sor@[0-9a-f]+$" 23 - enum: 24 - nvidia,tegra124-sor 25 - nvidia,tegra210-sor [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be: 5 - "nvidia,tegra20-pcie": for Tegra20 6 - "nvidia,tegra30-pcie": for Tegra30 7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 8 - "nvidia,tegra210-pcie": for Tegra210 9 - "nvidia,tegra186-pcie": for Tegra186 10 - power-domains: To ungate power partition by BPMP powergate driver. Must 13 - device_type: Must be "pci" 14 - reg: A list of physical base address and length for each set of controller 15 registers. Must contain an entry for each entry in the reg-names property. [all …]
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra124-nyan.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/thermal/thermal.h> 14 stdout-path = "serial0:115200n8"; 20 * missing a unit-address. However, the bootloader on these Chromebook 22 * Adding the unit-address causes the bootloader to create a /memory 34 /delete-node/ memory@80000000; 40 vdd-supply = <&vdd_3v3_hdmi>; 41 pll-supply = <&vdd_hdmi_pll>; 42 hdmi-supply = <&vdd_5v0_hdmi>; [all …]
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