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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-intel.c35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
96 if (priv->plat->max_speed == 2500) in intel_serdes_powerup()
249 priv->plat->max_speed = 2500; in intel_speed_mode_2500()
250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX; in intel_speed_mode_2500()
251 priv->plat->mdio_bus_data->xpcs_an_inband = false; in intel_speed_mode_2500()
253 priv->plat->max_speed = 1000; in intel_speed_mode_2500()
265 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; in intel_mgbe_ptp_clk_freq_config()
323 intel_priv = priv->plat->bsp_priv; in intel_crosststamp()
328 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN) in intel_crosststamp()
331 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
[all …]
H A Dstmmac_pci.c19 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
22 static void common_default_data(struct plat_stmmacenet_data *plat) in common_default_data() argument
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
25 plat->has_gmac = 1; in common_default_data()
26 plat->force_sf_dma_mode = 1; in common_default_data()
28 plat->mdio_bus_data->needs_reset = true; in common_default_data()
31 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
34 plat->unicast_filter_entries = 1; in common_default_data()
37 plat->maxmtu = JUMBO_LEN; in common_default_data()
40 plat->tx_queues_to_use = 1; in common_default_data()
[all …]
H A Dstmmac_platform.c129 * @plat: enet data
132 struct plat_stmmacenet_data *plat) in stmmac_mtl_setup() argument
144 plat->rx_queues_to_use = 1; in stmmac_mtl_setup()
145 plat->tx_queues_to_use = 1; in stmmac_mtl_setup()
151 plat->rx_queues_cfg[0].mode_to_use = MTL_QUEUE_DCB; in stmmac_mtl_setup()
152 plat->tx_queues_cfg[0].mode_to_use = MTL_QUEUE_DCB; in stmmac_mtl_setup()
166 &plat->rx_queues_to_use)) in stmmac_mtl_setup()
167 plat->rx_queues_to_use = 1; in stmmac_mtl_setup()
170 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; in stmmac_mtl_setup()
172 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_WSP; in stmmac_mtl_setup()
[all …]
H A Ddwmac-mediatek.c91 int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
92 int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
112 static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat) in mt2712_set_interface() argument
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
142 static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) in mt2712_delay_ps2stage() argument
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
[all …]
H A Ddwmac-loongson.c12 static int loongson_default_data(struct plat_stmmacenet_data *plat) in loongson_default_data() argument
14 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in loongson_default_data()
15 plat->has_gmac = 1; in loongson_default_data()
16 plat->force_sf_dma_mode = 1; in loongson_default_data()
19 plat->multicast_filter_bins = HASH_TABLE_SIZE; in loongson_default_data()
22 plat->unicast_filter_entries = 1; in loongson_default_data()
25 plat->maxmtu = JUMBO_LEN; in loongson_default_data()
28 plat->tx_queues_to_use = 1; in loongson_default_data()
29 plat->rx_queues_to_use = 1; in loongson_default_data()
32 plat->tx_queues_cfg[0].use_prio = false; in loongson_default_data()
[all …]
H A Dstmmac_ptp.c59 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; in stmmac_adjust_time()
71 if (priv->plat->est && priv->plat->est->enable) { in stmmac_adjust_time()
74 priv->plat->est->enable = false; in stmmac_adjust_time()
75 stmmac_est_configure(priv, priv->ioaddr, priv->plat->est, in stmmac_adjust_time()
76 priv->plat->clk_ptp_rate); in stmmac_adjust_time()
93 time.tv_nsec = priv->plat->est->btr_reserve[0]; in stmmac_adjust_time()
94 time.tv_sec = priv->plat->est->btr_reserve[1]; in stmmac_adjust_time()
96 cycle_time = (u64)priv->plat->est->ctr[1] * NSEC_PER_SEC + in stmmac_adjust_time()
97 priv->plat->est->ctr[0]; in stmmac_adjust_time()
102 priv->plat->est->btr[0] = (u32)time.tv_nsec; in stmmac_adjust_time()
[all …]
/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream() local
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
58 reg = readl(plat->regs + plat->ctl_reg); in socfpga_a10_clk_get_upstream()
61 if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) { in socfpga_a10_clk_get_upstream()
64 } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) { in socfpga_a10_clk_get_upstream()
77 *upclk = &plat->clks.clks[reg]; in socfpga_a10_clk_get_upstream()
83 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_endisable() local
[all …]
/openbmc/u-boot/drivers/gpio/
H A Ddwapb_gpio.c46 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); in dwapb_gpio_direction_input() local
48 clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); in dwapb_gpio_direction_input()
55 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); in dwapb_gpio_direction_output() local
57 setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
60 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
62 clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
69 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); in dwapb_gpio_get_value() local
70 return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin)); in dwapb_gpio_get_value()
76 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); in dwapb_gpio_set_value() local
79 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_set_value()
[all …]
H A Dmt7621_gpio.c46 static u32 reg_offs(struct mediatek_gpio_platdata *plat, int reg) in reg_offs() argument
48 return (reg * 0x10) + (plat->bank * 0x4); in reg_offs()
53 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); in mediatek_gpio_get_value() local
56 reg_offs(plat, GPIO_REG_DATA)) & BIT(offset)); in mediatek_gpio_get_value()
62 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); in mediatek_gpio_set_value() local
65 reg_offs(plat, value ? GPIO_REG_DSET : GPIO_REG_DCLR)); in mediatek_gpio_set_value()
72 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); in mediatek_gpio_direction_input() local
74 clrbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL), in mediatek_gpio_direction_input()
83 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); in mediatek_gpio_direction_output() local
85 setbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL), in mediatek_gpio_direction_output()
[all …]
H A Daltera_pio.c30 struct altera_pio_platdata *plat = dev_get_platdata(dev); in altera_pio_direction_input() local
31 struct altera_pio_regs *const regs = plat->regs; in altera_pio_direction_input()
41 struct altera_pio_platdata *plat = dev_get_platdata(dev); in altera_pio_direction_output() local
42 struct altera_pio_regs *const regs = plat->regs; in altera_pio_direction_output()
56 struct altera_pio_platdata *plat = dev_get_platdata(dev); in altera_pio_get_value() local
57 struct altera_pio_regs *const regs = plat->regs; in altera_pio_get_value()
65 struct altera_pio_platdata *plat = dev_get_platdata(dev); in altera_pio_set_value() local
66 struct altera_pio_regs *const regs = plat->regs; in altera_pio_set_value()
79 struct altera_pio_platdata *plat = dev_get_platdata(dev); in altera_pio_probe() local
81 uc_priv->gpio_count = plat->gpio_count; in altera_pio_probe()
[all …]
/openbmc/u-boot/drivers/power/pmic/
H A Di2c_pmic_emul.c31 struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul); in sandbox_i2c_pmic_read_data() local
33 if (plat->rw_idx + len > plat->buf_size) { in sandbox_i2c_pmic_read_data()
35 plat->reg_count); in sandbox_i2c_pmic_read_data()
40 (unsigned int)chip & 0xff, plat->rw_reg, plat->rw_idx, len); in sandbox_i2c_pmic_read_data()
42 memcpy(buffer, plat->reg + plat->rw_idx, len); in sandbox_i2c_pmic_read_data()
51 struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul); in sandbox_i2c_pmic_write_data() local
58 plat->rw_reg = *buffer; in sandbox_i2c_pmic_write_data()
59 plat->rw_idx = plat->rw_reg * plat->trans_len; in sandbox_i2c_pmic_write_data()
62 (unsigned int)chip & 0xff, plat->rw_reg, plat->rw_idx, len); in sandbox_i2c_pmic_write_data()
71 if (plat->rw_idx + len > plat->buf_size) { in sandbox_i2c_pmic_write_data()
[all …]
/openbmc/u-boot/drivers/rtc/
H A Di2c_rtc_emul.c52 struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); in sandbox_i2c_rtc_set_offset() local
55 old_offset = plat->offset; in sandbox_i2c_rtc_set_offset()
56 plat->use_system_time = use_system_time; in sandbox_i2c_rtc_set_offset()
58 plat->offset = offset; in sandbox_i2c_rtc_set_offset()
65 struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); in sandbox_i2c_rtc_get_set_base_time() local
68 old_base_time = plat->base_time; in sandbox_i2c_rtc_get_set_base_time()
70 plat->base_time = base_time; in sandbox_i2c_rtc_get_set_base_time()
77 struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); in reset_time() local
81 plat->base_time = rtc_mktime(&now); in reset_time()
82 plat->offset = 0; in reset_time()
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_lpuart.c136 struct lpuart_serial_platdata *plat = dev->platdata; in is_lpuart32() local
138 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; in is_lpuart32()
144 struct lpuart_serial_platdata *plat = dev_get_platdata(dev); in _lpuart_serial_setbrg() local
145 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_setbrg()
165 static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat) in _lpuart_serial_getc() argument
167 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_getc()
176 static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat, in _lpuart_serial_putc() argument
179 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_putc()
188 static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat) in _lpuart_serial_tstc() argument
190 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_tstc()
[all …]
H A Dserial_rockchip.c17 struct ns16550_platdata plat; member
23 struct ns16550_platdata plat; member
30 struct rockchip_uart_platdata *plat = dev_get_platdata(dev); in rockchip_serial_probe() local
33 plat->plat.base = plat->dtplat.reg[0]; in rockchip_serial_probe()
34 plat->plat.reg_shift = plat->dtplat.reg_shift; in rockchip_serial_probe()
35 plat->plat.clock = plat->dtplat.clock_frequency; in rockchip_serial_probe()
36 plat->plat.fcr = UART_FCR_DEFVAL; in rockchip_serial_probe()
37 dev->platdata = &plat->plat; in rockchip_serial_probe()
H A Dserial_stm32.c43 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev); in stm32_serial_setbrg() local
45 _stm32_serial_setbrg(plat->base, plat->uart_info, in stm32_serial_setbrg()
46 plat->clock_rate, baudrate); in stm32_serial_setbrg()
53 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev); in stm32_serial_setconfig() local
54 bool stm32f4 = plat->uart_info->stm32f4; in stm32_serial_setconfig()
55 u8 uart_enable_bit = plat->uart_info->uart_enable_bit; in stm32_serial_setconfig()
56 u32 cr1 = plat->base + CR1_OFFSET(stm32f4); in stm32_serial_setconfig()
101 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev); in stm32_serial_getc() local
102 bool stm32f4 = plat->uart_info->stm32f4; in stm32_serial_getc()
103 fdt_addr_t base = plat->base; in stm32_serial_getc()
[all …]
/openbmc/linux/drivers/media/platform/qcom/venus/
H A Dhfi_platform.c26 const struct hfi_platform *plat; in hfi_platform_get_codec_vpp_freq() local
29 plat = hfi_platform_get(version); in hfi_platform_get_codec_vpp_freq()
30 if (!plat) in hfi_platform_get_codec_vpp_freq()
33 if (plat->codec_vpp_freq) in hfi_platform_get_codec_vpp_freq()
34 freq = plat->codec_vpp_freq(session_type, codec); in hfi_platform_get_codec_vpp_freq()
42 const struct hfi_platform *plat; in hfi_platform_get_codec_vsp_freq() local
45 plat = hfi_platform_get(version); in hfi_platform_get_codec_vsp_freq()
46 if (!plat) in hfi_platform_get_codec_vsp_freq()
49 if (plat->codec_vpp_freq) in hfi_platform_get_codec_vsp_freq()
50 freq = plat->codec_vsp_freq(session_type, codec); in hfi_platform_get_codec_vsp_freq()
[all …]
/openbmc/linux/drivers/ata/
H A Dahci_mtk.c48 struct mtk_ahci_plat *plat = hpriv->plat_data; in mtk_ahci_platform_resets() local
52 plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi"); in mtk_ahci_platform_resets()
53 if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER) in mtk_ahci_platform_resets()
54 return PTR_ERR(plat->axi_rst); in mtk_ahci_platform_resets()
56 plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw"); in mtk_ahci_platform_resets()
57 if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER) in mtk_ahci_platform_resets()
58 return PTR_ERR(plat->sw_rst); in mtk_ahci_platform_resets()
60 plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg"); in mtk_ahci_platform_resets()
61 if (PTR_ERR(plat->reg_rst) == -EPROBE_DEFER) in mtk_ahci_platform_resets()
62 return PTR_ERR(plat->reg_rst); in mtk_ahci_platform_resets()
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Ddwc3-sti-glue.c45 static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_platdata *plat) in sti_dwc3_glue_drd_init() argument
49 val = readl(plat->syscfg_base + plat->syscfg_offset); in sti_dwc3_glue_drd_init()
53 switch (plat->mode) { in sti_dwc3_glue_drd_init()
73 pr_err("Unsupported mode of operation %d\n", plat->mode); in sti_dwc3_glue_drd_init()
76 writel(val, plat->syscfg_base + plat->syscfg_offset); in sti_dwc3_glue_drd_init()
81 static void sti_dwc3_glue_init(struct sti_dwc3_glue_platdata *plat) in sti_dwc3_glue_init() argument
85 reg = readl(plat->glue_base + CLKRST_CTRL); in sti_dwc3_glue_init()
90 writel(reg, plat->glue_base + CLKRST_CTRL); in sti_dwc3_glue_init()
93 reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1); in sti_dwc3_glue_init()
99 writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1); in sti_dwc3_glue_init()
[all …]
/openbmc/u-boot/drivers/video/
H A Dsandbox_sdl.c24 struct sandbox_sdl_plat *plat = dev_get_platdata(dev); in sandbox_sdl_probe() local
28 ret = sandbox_sdl_init_display(plat->xres, plat->yres, plat->bpix); in sandbox_sdl_probe()
33 uc_priv->xsize = plat->xres; in sandbox_sdl_probe()
34 uc_priv->ysize = plat->yres; in sandbox_sdl_probe()
35 uc_priv->bpix = plat->bpix; in sandbox_sdl_probe()
36 uc_priv->rot = plat->rot; in sandbox_sdl_probe()
37 uc_priv->vidconsole_drv_name = plat->vidconsole_drv_name; in sandbox_sdl_probe()
38 uc_priv->font_size = plat->font_size; in sandbox_sdl_probe()
46 struct sandbox_sdl_plat *plat = dev_get_platdata(dev); in sandbox_sdl_bind() local
51 plat->xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH); in sandbox_sdl_bind()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dcadence_qspi.c24 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_write_speed() local
32 plat->tshsl_ns, plat->tsd2d_ns, in cadence_spi_write_speed()
33 plat->tchsh_ns, plat->tslch_ns); in cadence_spi_write_speed()
120 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_set_speed() local
124 if (hz > plat->max_hz) in cadence_spi_set_speed()
125 hz = plat->max_hz; in cadence_spi_set_speed()
155 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_probe() local
158 priv->regbase = plat->regbase; in cadence_spi_probe()
159 priv->ahbbase = plat->ahbbase; in cadence_spi_probe()
162 cadence_qspi_apb_controller_init(plat); in cadence_spi_probe()
[all …]
H A Dsoft_spi.c41 struct soft_spi_platdata *plat = dev_get_platdata(bus); in soft_spi_scl() local
43 dm_gpio_set_value(&plat->sclk, bit); in soft_spi_scl()
51 struct soft_spi_platdata *plat = dev_get_platdata(bus); in soft_spi_sda() local
53 dm_gpio_set_value(&plat->mosi, bit); in soft_spi_sda()
61 struct soft_spi_platdata *plat = dev_get_platdata(bus); in soft_spi_cs_activate() local
63 dm_gpio_set_value(&plat->cs, 0); in soft_spi_cs_activate()
64 dm_gpio_set_value(&plat->sclk, 0); in soft_spi_cs_activate()
65 dm_gpio_set_value(&plat->cs, 1); in soft_spi_cs_activate()
73 struct soft_spi_platdata *plat = dev_get_platdata(bus); in soft_spi_cs_deactivate() local
75 dm_gpio_set_value(&plat->cs, 0); in soft_spi_cs_deactivate()
[all …]
/openbmc/linux/drivers/media/platform/mediatek/mdp3/
H A Dmtk-img-ipi.h119 #define CFG_CHECK(plat, p_id) ((plat) == (p_id)) argument
121 #define _CFG_OFST(plat, cfg, ofst) ((void *)(&((cfg)->config_##plat) + (ofst))) argument
122 #define CFG_OFST(plat, cfg, ofst) \ argument
123 (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_OFST(plat, cfg, ofst))
125 #define _CFG_ADDR(plat, cfg, mem) (&((cfg)->config_##plat.mem)) argument
126 #define CFG_ADDR(plat, cfg, mem) \ argument
127 (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_ADDR(plat, cfg, mem))
129 #define _CFG_GET(plat, cfg, mem) ((cfg)->config_##plat.mem) argument
130 #define CFG_GET(plat, cfg, mem) \ argument
131 (IS_ERR_OR_NULL(cfg) ? 0 : _CFG_GET(plat, cfg, mem))
[all …]
/openbmc/u-boot/drivers/misc/
H A Di2c_eeprom_emul.c35 struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev); in sandbox_i2c_eeprom_set_test_mode() local
37 plat->test_mode = mode; in sandbox_i2c_eeprom_set_test_mode()
42 struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev); in sandbox_i2c_eeprom_set_offset_len() local
44 plat->offset_len = offset_len; in sandbox_i2c_eeprom_set_offset_len()
56 struct sandbox_i2c_flash_plat_data *plat = in sandbox_i2c_eeprom_xfer() local
61 if (!plat->size) in sandbox_i2c_eeprom_xfer()
63 if (msg->addr + msg->len > plat->size) { in sandbox_i2c_eeprom_xfer()
65 __func__, msg->addr, msg->len, plat->size); in sandbox_i2c_eeprom_xfer()
73 if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE) in sandbox_i2c_eeprom_xfer()
79 } else if (len >= plat->offset_len) { in sandbox_i2c_eeprom_xfer()
[all …]
H A Dspltest_sandbox.c13 struct dtd_sandbox_spl_test *plat = dev_get_platdata(dev); in sandbox_spl_probe() local
17 printf("bool %d\n", plat->boolval); in sandbox_spl_probe()
19 printf("byte %02x\n", plat->byteval); in sandbox_spl_probe()
21 for (i = 0; i < sizeof(plat->bytearray); i++) in sandbox_spl_probe()
22 printf(" %02x", plat->bytearray[i]); in sandbox_spl_probe()
25 printf("int %d\n", plat->intval); in sandbox_spl_probe()
27 for (i = 0; i < ARRAY_SIZE(plat->intarray); i++) in sandbox_spl_probe()
28 printf(" %d", plat->intarray[i]); in sandbox_spl_probe()
32 for (i = 0; i < sizeof(plat->longbytearray); i++) in sandbox_spl_probe()
33 printf(" %02x", plat->longbytearray[i]); in sandbox_spl_probe()
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/openbmc/u-boot/drivers/mmc/
H A Dsdhci-cadence.c86 static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, in sdhci_cdns_write_phy_reg() argument
89 void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04; in sdhci_cdns_write_phy_reg()
110 static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, in sdhci_cdns_phy_init() argument
122 ret = sdhci_cdns_write_phy_reg(plat, in sdhci_cdns_phy_init()
135 struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev); in sdhci_cdns_set_control_reg() local
158 tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06); in sdhci_cdns_set_control_reg()
161 writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06); in sdhci_cdns_set_control_reg()
168 static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, in sdhci_cdns_set_tune_val() argument
171 void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06; in sdhci_cdns_set_tune_val()
190 struct sdhci_cdns_plat *plat = dev_get_platdata(dev); in sdhci_cdns_execute_tuning() local
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