Lines Matching full:plat
35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
96 if (priv->plat->max_speed == 2500) in intel_serdes_powerup()
249 priv->plat->max_speed = 2500; in intel_speed_mode_2500()
250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX; in intel_speed_mode_2500()
251 priv->plat->mdio_bus_data->xpcs_an_inband = false; in intel_speed_mode_2500()
253 priv->plat->max_speed = 1000; in intel_speed_mode_2500()
265 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; in intel_mgbe_ptp_clk_freq_config()
323 intel_priv = priv->plat->bsp_priv; in intel_crosststamp()
328 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN) in intel_crosststamp()
331 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
337 switch (priv->plat->int_snapshot_num) { in intel_crosststamp()
352 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
378 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
397 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
417 static void common_default_data(struct plat_stmmacenet_data *plat) in common_default_data() argument
419 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
420 plat->has_gmac = 1; in common_default_data()
421 plat->force_sf_dma_mode = 1; in common_default_data()
423 plat->mdio_bus_data->needs_reset = true; in common_default_data()
426 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
429 plat->unicast_filter_entries = 1; in common_default_data()
432 plat->maxmtu = JUMBO_LEN; in common_default_data()
435 plat->tx_queues_to_use = 1; in common_default_data()
436 plat->rx_queues_to_use = 1; in common_default_data()
439 plat->tx_queues_cfg[0].use_prio = false; in common_default_data()
440 plat->rx_queues_cfg[0].use_prio = false; in common_default_data()
443 plat->rx_queues_cfg[0].pkt_route = 0x0; in common_default_data()
447 struct plat_stmmacenet_data *plat) in intel_mgbe_common_data() argument
454 plat->pdev = pdev; in intel_mgbe_common_data()
455 plat->phy_addr = -1; in intel_mgbe_common_data()
456 plat->clk_csr = 5; in intel_mgbe_common_data()
457 plat->has_gmac = 0; in intel_mgbe_common_data()
458 plat->has_gmac4 = 1; in intel_mgbe_common_data()
459 plat->force_sf_dma_mode = 0; in intel_mgbe_common_data()
460 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE); in intel_mgbe_common_data()
471 plat->mult_fact_100ns = 1; in intel_mgbe_common_data()
473 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; in intel_mgbe_common_data()
475 for (i = 0; i < plat->rx_queues_to_use; i++) { in intel_mgbe_common_data()
476 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
477 plat->rx_queues_cfg[i].chan = i; in intel_mgbe_common_data()
480 plat->rx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
483 plat->rx_queues_cfg[i].pkt_route = 0x0; in intel_mgbe_common_data()
486 for (i = 0; i < plat->tx_queues_to_use; i++) { in intel_mgbe_common_data()
487 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
490 plat->tx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
493 plat->tx_queues_cfg[i].tbs_en = 1; in intel_mgbe_common_data()
497 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; in intel_mgbe_common_data()
498 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; in intel_mgbe_common_data()
500 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; in intel_mgbe_common_data()
501 plat->tx_queues_cfg[0].weight = 0x09; in intel_mgbe_common_data()
502 plat->tx_queues_cfg[1].weight = 0x0A; in intel_mgbe_common_data()
503 plat->tx_queues_cfg[2].weight = 0x0B; in intel_mgbe_common_data()
504 plat->tx_queues_cfg[3].weight = 0x0C; in intel_mgbe_common_data()
505 plat->tx_queues_cfg[4].weight = 0x0D; in intel_mgbe_common_data()
506 plat->tx_queues_cfg[5].weight = 0x0E; in intel_mgbe_common_data()
507 plat->tx_queues_cfg[6].weight = 0x0F; in intel_mgbe_common_data()
508 plat->tx_queues_cfg[7].weight = 0x10; in intel_mgbe_common_data()
510 plat->dma_cfg->pbl = 32; in intel_mgbe_common_data()
511 plat->dma_cfg->pblx8 = true; in intel_mgbe_common_data()
512 plat->dma_cfg->fixed_burst = 0; in intel_mgbe_common_data()
513 plat->dma_cfg->mixed_burst = 0; in intel_mgbe_common_data()
514 plat->dma_cfg->aal = 0; in intel_mgbe_common_data()
515 plat->dma_cfg->dche = true; in intel_mgbe_common_data()
517 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), in intel_mgbe_common_data()
519 if (!plat->axi) in intel_mgbe_common_data()
522 plat->axi->axi_lpi_en = 0; in intel_mgbe_common_data()
523 plat->axi->axi_xit_frm = 0; in intel_mgbe_common_data()
524 plat->axi->axi_wr_osr_lmt = 1; in intel_mgbe_common_data()
525 plat->axi->axi_rd_osr_lmt = 1; in intel_mgbe_common_data()
526 plat->axi->axi_blen[0] = 4; in intel_mgbe_common_data()
527 plat->axi->axi_blen[1] = 8; in intel_mgbe_common_data()
528 plat->axi->axi_blen[2] = 16; in intel_mgbe_common_data()
530 plat->ptp_max_adj = plat->clk_ptp_rate; in intel_mgbe_common_data()
531 plat->eee_usecs_rate = plat->clk_ptp_rate; in intel_mgbe_common_data()
536 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, in intel_mgbe_common_data()
538 plat->clk_ptp_rate); in intel_mgbe_common_data()
540 if (IS_ERR(plat->stmmac_clk)) { in intel_mgbe_common_data()
542 plat->stmmac_clk = NULL; in intel_mgbe_common_data()
545 ret = clk_prepare_enable(plat->stmmac_clk); in intel_mgbe_common_data()
547 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_mgbe_common_data()
551 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; in intel_mgbe_common_data()
554 plat->multicast_filter_bins = HASH_TABLE_SIZE; in intel_mgbe_common_data()
557 plat->unicast_filter_entries = 1; in intel_mgbe_common_data()
560 plat->maxmtu = JUMBO_LEN; in intel_mgbe_common_data()
562 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN; in intel_mgbe_common_data()
565 plat->vlan_fail_q = plat->rx_queues_to_use - 1; in intel_mgbe_common_data()
579 plat->phy_interface = phy_mode; in intel_mgbe_common_data()
586 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII || in intel_mgbe_common_data()
587 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { in intel_mgbe_common_data()
588 plat->mdio_bus_data->has_xpcs = true; in intel_mgbe_common_data()
589 plat->mdio_bus_data->xpcs_an_inband = true; in intel_mgbe_common_data()
598 plat->mdio_bus_data->xpcs_an_inband = false; in intel_mgbe_common_data()
604 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; in intel_mgbe_common_data()
605 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; in intel_mgbe_common_data()
607 plat->int_snapshot_num = AUX_SNAPSHOT1; in intel_mgbe_common_data()
608 plat->ext_snapshot_num = AUX_SNAPSHOT0; in intel_mgbe_common_data()
610 plat->crosststamp = intel_crosststamp; in intel_mgbe_common_data()
611 plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_mgbe_common_data()
614 plat->msi_mac_vec = 29; in intel_mgbe_common_data()
615 plat->msi_lpi_vec = 28; in intel_mgbe_common_data()
616 plat->msi_sfty_ce_vec = 27; in intel_mgbe_common_data()
617 plat->msi_sfty_ue_vec = 26; in intel_mgbe_common_data()
618 plat->msi_rx_base_vec = 0; in intel_mgbe_common_data()
619 plat->msi_tx_base_vec = 1; in intel_mgbe_common_data()
625 struct plat_stmmacenet_data *plat) in ehl_common_data() argument
627 plat->rx_queues_to_use = 8; in ehl_common_data()
628 plat->tx_queues_to_use = 8; in ehl_common_data()
629 plat->flags |= STMMAC_FLAG_USE_PHY_WOL; in ehl_common_data()
630 plat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY; in ehl_common_data()
632 plat->safety_feat_cfg->tsoee = 1; in ehl_common_data()
633 plat->safety_feat_cfg->mrxpee = 1; in ehl_common_data()
634 plat->safety_feat_cfg->mestee = 1; in ehl_common_data()
635 plat->safety_feat_cfg->mrxee = 1; in ehl_common_data()
636 plat->safety_feat_cfg->mtxee = 1; in ehl_common_data()
637 plat->safety_feat_cfg->epsi = 0; in ehl_common_data()
638 plat->safety_feat_cfg->edpp = 0; in ehl_common_data()
639 plat->safety_feat_cfg->prtyen = 0; in ehl_common_data()
640 plat->safety_feat_cfg->tmouten = 0; in ehl_common_data()
642 return intel_mgbe_common_data(pdev, plat); in ehl_common_data()
646 struct plat_stmmacenet_data *plat) in ehl_sgmii_data() argument
648 plat->bus_id = 1; in ehl_sgmii_data()
649 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_sgmii_data()
650 plat->speed_mode_2500 = intel_speed_mode_2500; in ehl_sgmii_data()
651 plat->serdes_powerup = intel_serdes_powerup; in ehl_sgmii_data()
652 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_sgmii_data()
654 plat->clk_ptp_rate = 204800000; in ehl_sgmii_data()
656 return ehl_common_data(pdev, plat); in ehl_sgmii_data()
664 struct plat_stmmacenet_data *plat) in ehl_rgmii_data() argument
666 plat->bus_id = 1; in ehl_rgmii_data()
667 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; in ehl_rgmii_data()
669 plat->clk_ptp_rate = 204800000; in ehl_rgmii_data()
671 return ehl_common_data(pdev, plat); in ehl_rgmii_data()
679 struct plat_stmmacenet_data *plat) in ehl_pse0_common_data() argument
681 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_pse0_common_data()
684 plat->bus_id = 2; in ehl_pse0_common_data()
685 plat->host_dma_width = 32; in ehl_pse0_common_data()
687 plat->clk_ptp_rate = 200000000; in ehl_pse0_common_data()
691 return ehl_common_data(pdev, plat); in ehl_pse0_common_data()
695 struct plat_stmmacenet_data *plat) in ehl_pse0_rgmii1g_data() argument
697 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse0_rgmii1g_data()
698 return ehl_pse0_common_data(pdev, plat); in ehl_pse0_rgmii1g_data()
706 struct plat_stmmacenet_data *plat) in ehl_pse0_sgmii1g_data() argument
708 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse0_sgmii1g_data()
709 plat->speed_mode_2500 = intel_speed_mode_2500; in ehl_pse0_sgmii1g_data()
710 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse0_sgmii1g_data()
711 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse0_sgmii1g_data()
712 return ehl_pse0_common_data(pdev, plat); in ehl_pse0_sgmii1g_data()
720 struct plat_stmmacenet_data *plat) in ehl_pse1_common_data() argument
722 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_pse1_common_data()
725 plat->bus_id = 3; in ehl_pse1_common_data()
726 plat->host_dma_width = 32; in ehl_pse1_common_data()
728 plat->clk_ptp_rate = 200000000; in ehl_pse1_common_data()
732 return ehl_common_data(pdev, plat); in ehl_pse1_common_data()
736 struct plat_stmmacenet_data *plat) in ehl_pse1_rgmii1g_data() argument
738 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse1_rgmii1g_data()
739 return ehl_pse1_common_data(pdev, plat); in ehl_pse1_rgmii1g_data()
747 struct plat_stmmacenet_data *plat) in ehl_pse1_sgmii1g_data() argument
749 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse1_sgmii1g_data()
750 plat->speed_mode_2500 = intel_speed_mode_2500; in ehl_pse1_sgmii1g_data()
751 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse1_sgmii1g_data()
752 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse1_sgmii1g_data()
753 return ehl_pse1_common_data(pdev, plat); in ehl_pse1_sgmii1g_data()
761 struct plat_stmmacenet_data *plat) in tgl_common_data() argument
763 plat->rx_queues_to_use = 6; in tgl_common_data()
764 plat->tx_queues_to_use = 4; in tgl_common_data()
765 plat->clk_ptp_rate = 204800000; in tgl_common_data()
766 plat->speed_mode_2500 = intel_speed_mode_2500; in tgl_common_data()
768 plat->safety_feat_cfg->tsoee = 1; in tgl_common_data()
769 plat->safety_feat_cfg->mrxpee = 0; in tgl_common_data()
770 plat->safety_feat_cfg->mestee = 1; in tgl_common_data()
771 plat->safety_feat_cfg->mrxee = 1; in tgl_common_data()
772 plat->safety_feat_cfg->mtxee = 1; in tgl_common_data()
773 plat->safety_feat_cfg->epsi = 0; in tgl_common_data()
774 plat->safety_feat_cfg->edpp = 0; in tgl_common_data()
775 plat->safety_feat_cfg->prtyen = 0; in tgl_common_data()
776 plat->safety_feat_cfg->tmouten = 0; in tgl_common_data()
778 return intel_mgbe_common_data(pdev, plat); in tgl_common_data()
782 struct plat_stmmacenet_data *plat) in tgl_sgmii_phy0_data() argument
784 plat->bus_id = 1; in tgl_sgmii_phy0_data()
785 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in tgl_sgmii_phy0_data()
786 plat->serdes_powerup = intel_serdes_powerup; in tgl_sgmii_phy0_data()
787 plat->serdes_powerdown = intel_serdes_powerdown; in tgl_sgmii_phy0_data()
788 return tgl_common_data(pdev, plat); in tgl_sgmii_phy0_data()
796 struct plat_stmmacenet_data *plat) in tgl_sgmii_phy1_data() argument
798 plat->bus_id = 2; in tgl_sgmii_phy1_data()
799 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in tgl_sgmii_phy1_data()
800 plat->serdes_powerup = intel_serdes_powerup; in tgl_sgmii_phy1_data()
801 plat->serdes_powerdown = intel_serdes_powerdown; in tgl_sgmii_phy1_data()
802 return tgl_common_data(pdev, plat); in tgl_sgmii_phy1_data()
810 struct plat_stmmacenet_data *plat) in adls_sgmii_phy0_data() argument
812 plat->bus_id = 1; in adls_sgmii_phy0_data()
813 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in adls_sgmii_phy0_data()
817 return tgl_common_data(pdev, plat); in adls_sgmii_phy0_data()
825 struct plat_stmmacenet_data *plat) in adls_sgmii_phy1_data() argument
827 plat->bus_id = 2; in adls_sgmii_phy1_data()
828 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in adls_sgmii_phy1_data()
832 return tgl_common_data(pdev, plat); in adls_sgmii_phy1_data()
902 struct plat_stmmacenet_data *plat) in quark_default_data() argument
907 common_default_data(plat); in quark_default_data()
925 plat->bus_id = pci_dev_id(pdev); in quark_default_data()
926 plat->phy_addr = ret; in quark_default_data()
927 plat->phy_interface = PHY_INTERFACE_MODE_RMII; in quark_default_data()
929 plat->dma_cfg->pbl = 16; in quark_default_data()
930 plat->dma_cfg->pblx8 = true; in quark_default_data()
931 plat->dma_cfg->fixed_burst = 1; in quark_default_data()
942 struct plat_stmmacenet_data *plat, in stmmac_config_single_msi() argument
956 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; in stmmac_config_single_msi()
964 struct plat_stmmacenet_data *plat, in stmmac_config_multi_msi() argument
970 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX || in stmmac_config_multi_msi()
971 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) { in stmmac_config_multi_msi()
986 for (i = 0; i < plat->rx_queues_to_use; i++) { in stmmac_config_multi_msi()
988 plat->msi_rx_base_vec + i * 2); in stmmac_config_multi_msi()
992 for (i = 0; i < plat->tx_queues_to_use; i++) { in stmmac_config_multi_msi()
994 plat->msi_tx_base_vec + i * 2); in stmmac_config_multi_msi()
997 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
998 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec); in stmmac_config_multi_msi()
999 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1000 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec); in stmmac_config_multi_msi()
1001 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1002 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec); in stmmac_config_multi_msi()
1003 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1004 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec); in stmmac_config_multi_msi()
1005 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1006 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec); in stmmac_config_multi_msi()
1008 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; in stmmac_config_multi_msi()
1031 struct plat_stmmacenet_data *plat; in intel_eth_pci_probe() local
1039 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); in intel_eth_pci_probe()
1040 if (!plat) in intel_eth_pci_probe()
1043 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, in intel_eth_pci_probe()
1044 sizeof(*plat->mdio_bus_data), in intel_eth_pci_probe()
1046 if (!plat->mdio_bus_data) in intel_eth_pci_probe()
1049 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), in intel_eth_pci_probe()
1051 if (!plat->dma_cfg) in intel_eth_pci_probe()
1054 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, in intel_eth_pci_probe()
1055 sizeof(*plat->safety_feat_cfg), in intel_eth_pci_probe()
1057 if (!plat->safety_feat_cfg) in intel_eth_pci_probe()
1074 plat->bsp_priv = intel_priv; in intel_eth_pci_probe()
1082 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1083 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1084 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1085 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1086 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1087 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1088 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1090 ret = info->setup(pdev, plat); in intel_eth_pci_probe()
1097 if (plat->eee_usecs_rate > 0) { in intel_eth_pci_probe()
1100 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; in intel_eth_pci_probe()
1104 ret = stmmac_config_multi_msi(pdev, plat, &res); in intel_eth_pci_probe()
1106 ret = stmmac_config_single_msi(pdev, plat, &res); in intel_eth_pci_probe()
1114 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); in intel_eth_pci_probe()
1122 clk_disable_unprepare(plat->stmmac_clk); in intel_eth_pci_probe()
1123 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_eth_pci_probe()
1141 clk_disable_unprepare(priv->plat->stmmac_clk); in intel_eth_pci_remove()
1142 clk_unregister_fixed_rate(priv->plat->stmmac_clk); in intel_eth_pci_remove()