Home
last modified time | relevance | path

Searched full:pl022 (Results 1 – 25 of 69) sorted by relevance

123

/openbmc/linux/drivers/spi/
H A Dspi-pl022.c3 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
12 * Initial adoption to PL022 by:
27 #include <linux/amba/pl022.h>
312 * for PL022 derivates
333 * struct pl022 - This is the private SSP driver data structure
367 struct pl022 { struct
433 * @pl022: SSP driver private data structure
440 static void internal_cs_control(struct pl022 *pl022, u32 command) in internal_cs_control() argument
444 tmp = readw(SSP_CSR(pl022->virtbase)); in internal_cs_control()
446 tmp &= ~BIT(pl022->cur_cs); in internal_cs_control()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-pl022.yaml4 $id: http://devicetree.org/schemas/spi/spi-pl022.yaml#
7 title: ARM PL022 SPI controller
21 const: arm,pl022
28 - const: arm,pl022
45 pl022,autosuspend-delay:
51 pl022,rt:
83 pl022,interface:
91 pl022,com-mode:
100 pl022,rx-level-trig:
106 pl022,tx-level-trig:
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2-svk.dts116 pl022,hierarchy = <0>;
117 pl022,interface = <0>;
118 pl022,slave-tx-disable = <0>;
119 pl022,com-mode = <0>;
120 pl022,rx-level-trig = <1>;
121 pl022,tx-level-trig = <1>;
122 pl022,ctrl-len = <11>;
123 pl022,wait-state = <0>;
124 pl022,duplex = <0>;
140 pl022,hierarchy = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear1310-evb.dts355 pl022,hierarchy = <0>;
356 pl022,interface = <0>;
357 pl022,slave-tx-disable;
358 pl022,com-mode = <0>;
359 pl022,rx-level-trig = <0>;
360 pl022,tx-level-trig = <0>;
361 pl022,ctrl-len = <0x7>;
362 pl022,wait-state = <0>;
363 pl022,duplex = <0>;
388 pl022,hierarchy = <0>;
[all …]
H A Dspear1340-evb.dts448 pl022,hierarchy = <0>;
449 pl022,interface = <0>;
450 pl022,slave-tx-disable;
451 pl022,com-mode = <0x2>;
452 pl022,rx-level-trig = <0>;
453 pl022,tx-level-trig = <0>;
454 pl022,ctrl-len = <0x11>;
455 pl022,wait-state = <0>;
456 pl022,duplex = <0>;
464 pl022,hierarchy = <0>;
[all …]
H A Dspear600.dtsi212 compatible = "arm,pl022", "arm,primecell";
222 compatible = "arm,pl022", "arm,primecell";
232 compatible = "arm,pl022", "arm,primecell";
H A Dspear320.dtsi61 compatible = "arm,pl022", "arm,primecell";
71 compatible = "arm,pl022", "arm,primecell";
/openbmc/qemu/include/hw/ssi/
H A Dpl022.h2 * ARM PrimeCell PL022 Synchronous Serial Port
13 * This is a model of the Arm PrimeCell PL022 synchronous serial port.
14 * The PL022 TRM is:
28 #define TYPE_PL022 "pl022"
29 OBJECT_DECLARE_SIMPLE_TYPE(PL022State, PL022)
/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-overdrive-rev-b0.dts67 pl022,hierarchy = <0>;
68 pl022,interface = <0>;
69 pl022,com-mode = <0x0>;
70 pl022,rx-level-trig = <0>;
71 pl022,tx-level-trig = <0>;
H A Damd-overdrive-rev-b1.dts79 pl022,hierarchy = <0>;
80 pl022,interface = <0>;
81 pl022,com-mode = <0x0>;
82 pl022,rx-level-trig = <0>;
83 pl022,tx-level-trig = <0>;
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc3250-phy3250.dts208 pl022,interface = <0>;
209 pl022,com-mode = <0>;
210 pl022,rx-level-trig = <1>;
211 pl022,tx-level-trig = <1>;
212 pl022,ctrl-len = <11>;
213 pl022,wait-state = <0>;
214 pl022,duplex = <0>;
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dspear_spics.txt3 SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
5 PL022 control. If chipselect remain under PL022 control then they would be
12 directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
/openbmc/qemu/hw/ssi/
H A Dpl022.c2 * Arm PrimeCell PL022 Synchronous Serial Port
14 #include "hw/ssi/pl022.h"
23 do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
25 do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
29 do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
208 qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n"); in pl022_write()
219 PL022State *s = PL022(dev); in pl022_reset()
287 PL022State *s = PL022(dev); in pl022_realize()
289 memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000); in pl022_realize()
H A DKconfig1 config PL022 config
/openbmc/u-boot/drivers/spi/
H A Dpl022_spi.c9 * Driver for ARM PL022 SPI Controller.
74 * ARM PL022 exists in different 'flavors'.
80 /* PL022 version is 0x00041022 */ in pl022_is_supported()
98 /* Check the PL022 version */ in pl022_spi_probe()
309 { .compatible = "arm,pl022-spi" },
H A DKconfig182 bool "ARM AMBA PL022 SSP controller driver"
185 This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP
187 bus and a PL022 controller, say Y or M here.
/openbmc/linux/arch/arm/mach-spear/
H A Dspear320.c13 #include <linux/amba/pl022.h>
218 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
222 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
224 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
/openbmc/linux/arch/arm64/boot/dts/toshiba/
H A Dtmpv7708.dtsi355 compatible = "arm,pl022", "arm,primecell";
369 compatible = "arm,pl022", "arm,primecell";
383 compatible = "arm,pl022", "arm,primecell";
397 compatible = "arm,pl022", "arm,primecell";
411 compatible = "arm,pl022", "arm,primecell";
425 compatible = "arm,pl022", "arm,primecell";
439 compatible = "arm,pl022", "arm,primecell";
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3519.dtsi127 compatible = "arm,pl022", "arm,primecell";
139 compatible = "arm,pl022", "arm,primecell";
151 compatible = "arm,pl022", "arm,primecell";
/openbmc/linux/drivers/gpio/
H A Dgpio-spear-spics.c21 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
22 * through system registers. This register lies outside spi (pl022)
26 * (out of 4 possible chipselects in pl022) can be made low to select
/openbmc/linux/include/linux/amba/
H A Dpl022.h3 * include/linux/amba/pl022.h
12 * Initial adoption to PL022 by:
65 * this feature is only available in ST versionf of PL022
/openbmc/qemu/hw/arm/
H A DKconfig79 select PL022 # SPI
228 select PL022 # SPI
560 select PL022 # SPI
/openbmc/u-boot/include/dm/platform_data/
H A Dspi_pl022.h6 * Structure for use with U_BOOT_DEVICE for pl022 SPI devices or to use
/openbmc/qemu/docs/system/arm/
H A Dhighbank.rst17 - PL022 synchronous serial port controller
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi450 compatible = "arm,pl022", "arm,primecell";
465 compatible = "arm,pl022", "arm,primecell";
480 compatible = "arm,pl022", "arm,primecell";
680 compatible = "arm,pl022", "arm,primecell";
695 compatible = "arm,pl022", "arm,primecell";
710 compatible = "arm,pl022", "arm,primecell";
725 compatible = "arm,pl022", "arm,primecell";

123