| /openbmc/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | pinmux.c | 10 #define PIN(pin, f0, f1, f2, f3) \ macro
23 /* pin, f0, f1, f2, f3 */
25 PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
26 PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
27 PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
28 PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
29 PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
30 PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
31 PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
32 PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | pinmux.c | 10 #define PIN(pin, f0, f1, f2, f3) \ macro
23 /* pin, f0, f1, f2, f3 */
25 PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
26 PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
27 PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
28 PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
29 PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
30 PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
33 PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
34 PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | pinmux.c | 10 #define PIN(pin, f0, f1, f2, f3) \ macro
23 /* pin, f0, f1, f2, f3 */
25 PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
26 PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
27 PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
28 PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
29 PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
30 PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
31 PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
32 PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | pinmux.c | 10 #define PIN(pin, f0, f1, f2, f3) \ macro
23 /* pin, f0, f1, f2, f3 */
25 PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
26 PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
27 PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
28 PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
29 PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
30 PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
31 PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
32 PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
[all …]
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | sama5d3_lcd.dtsi | 42 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
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| H A D | at91sam9x5_lcd.dtsi | 42 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
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| /openbmc/u-boot/board/sunxi/ |
| H A D | gmac.c | 11 int pin; local
35 /* Configure pin mux settings for GMAC */
37 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
39 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
43 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
46 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
47 sunxi_gpio_set_drv(pin, 3);
50 /* Configure sun6i RGMII mode pin mux settings */
51 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
52 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
[all …]
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| H A D | board.c | 41 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
51 printf("Error invalid soft i2c sda pin: '%s', err %d\n", in soft_i2c_board_init()
57 printf("Error requesting soft i2c sda pin: '%s', err %d\n", in soft_i2c_board_init()
64 printf("Error invalid soft i2c scl pin: '%s', err %d\n", in soft_i2c_board_init()
70 printf("Error requesting soft i2c scl pin: '%s', err %d\n", in soft_i2c_board_init()
334 unsigned int pin; in nand_pinmux_setup() local
336 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) in nand_pinmux_setup()
337 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); in nand_pinmux_setup()
340 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) in nand_pinmux_setup()
341 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); in nand_pinmux_setup()
[all …]
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| /openbmc/u-boot/drivers/gpio/ |
| H A D | kw_gpio.c | 24 void __set_direction(unsigned pin, int input) in __set_direction() argument
28 u = readl(GPIO_IO_CONF(pin)); in __set_direction()
30 u |= 1 << (pin & 31); in __set_direction()
32 u &= ~(1 << (pin & 31)); in __set_direction()
33 writel(u, GPIO_IO_CONF(pin)); in __set_direction()
35 u = readl(GPIO_IO_CONF(pin)); in __set_direction()
38 static void __set_level(unsigned pin, int high) in __set_level() argument
42 u = readl(GPIO_OUT(pin)); in __set_level()
44 u |= 1 << (pin & 31); in __set_level()
46 u &= ~(1 << (pin & 31)); in __set_level()
[all …]
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| H A D | at91_gpio.c | 58 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) in at91_set_pio_pullup() argument
62 if (at91_port && (pin < GPIO_PER_BANK)) in at91_set_pio_pullup()
63 at91_set_port_pullup(at91_port, pin, use_pullup); in at91_set_pio_pullup()
69 * mux the pin to the "GPIO" peripheral role.
71 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) in at91_set_pio_periph() argument
76 if (at91_port && (pin < GPIO_PER_BANK)) { in at91_set_pio_periph()
77 mask = 1 << pin; in at91_set_pio_periph()
79 at91_set_pio_pullup(port, pin, use_pullup); in at91_set_pio_periph()
87 * mux the pin to the "A" internal peripheral role.
89 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) in at91_set_a_periph() argument
[all …]
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| /openbmc/u-boot/drivers/pinctrl/renesas/ |
| H A D | Kconfig | 4 bool "Renesas pin control drivers"
10 bool "Renesas RCar Gen2 R8A7790 pin control driver"
13 Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs.
16 the GPIO definitions and pin control functions for each available
20 bool "Renesas RCar Gen2 R8A7791 pin control driver"
23 Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs.
26 the GPIO definitions and pin control functions for each available
30 bool "Renesas RCar Gen2 R8A7792 pin control driver"
33 Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs.
36 the GPIO definitions and pin control functions for each available
[all …]
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| /openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/ |
| H A D | gpio.h | 18 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) argument
19 #define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) argument
20 #define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) argument
21 #define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) argument
22 #define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) argument
23 #define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) argument
24 #define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) argument
25 #define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) argument
26 #define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) argument
32 void kw_gpio_set_valid(unsigned pin, int mode);
[all …]
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| /openbmc/u-boot/drivers/pinctrl/ |
| H A D | Kconfig | 5 menu "Pin controllers"
8 bool "Support pin controllers"
15 bool "Support full pin controllers"
31 bool "Support generic pin controllers"
38 some pin configuration parameters. It would be easier if you only
39 need the generic DT interface for pin muxing and pin configuration.
45 bool "Support pin multiplexing controllers"
49 This option enables pin multiplexing through the generic pinctrl
51 a single pin can be used for several functions. An SoC pinctrl driver
52 allows the required function to be selected for each pin.
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | pinmux.c | 6 /* Tegra20 pin multiplexing functions */
13 * This defines the order of the pin mux control bits in the registers. For
14 * some reason there is no correspendence between the tristate, pin mux and
256 /* Convenient macro for defining pin group properties */
269 /* A normal pin group where the mux name and pull-up name match */
270 #define PIN(pingrp, f0, f1, f2, f3) \ macro
273 /* A pin group where the pull-up name doesn't have a 1-1 mapping */
277 /* A pin group number which is not used */
279 PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
285 PIN(ATA, IDE, NAND, GMI, RSVD4),
[all …]
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| /openbmc/u-boot/drivers/pinctrl/meson/ |
| H A D | pinctrl-meson-gxl.c | 19 PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
20 PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
21 PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
23 static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
24 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
25 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
27 static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) };
28 static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) };
29 static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) };
30 static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) };
[all …]
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| H A D | pinctrl-meson-gxbb.c | 19 PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
20 PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
21 PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
23 static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
24 static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
25 static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
27 static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
28 static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
29 static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
30 static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/pinctrl/ |
| H A D | pinctrl-bindings.txt | 3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
21 for client device device tree nodes to map those state names to the pin
24 Note that pin controllers themselves may also be client devices of themselves.
25 For example, a pin controller may set up its own "active" state when the
[all …]
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| /openbmc/u-boot/drivers/pinctrl/mscc/ |
| H A D | Kconfig | 10 bool "Microsemi ocelot family pin control driver"
12 Support pin multiplexing and pin configuration control on
19 bool "Microsemi luton family pin control driver"
21 Support pin multiplexing and pin configuration control on
28 bool "Microsemi jr2 family pin control driver"
30 Support pin multiplexing and pin configuration control on
37 bool "Microsemi servalt family pin control driver"
39 Support pin multiplexing and pin configuration control on
46 bool "Microsemi serval family pin control driver"
48 Support pin multiplexing and pin configuration control on
|
| /openbmc/qemu/tests/qtest/ |
| H A D | stm32l4x5_gpio-test.c | 86 static inline void *test_data(uint32_t gpio_addr, uint8_t pin) in test_data() argument
88 return (void *)(uintptr_t)((gpio_addr & GPIO_ADDR_MASK) | (pin & PIN_MASK)); in test_data()
105 unsigned int pin, uint32_t value) in gpio_set_bit() argument
107 uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin); in gpio_set_bit()
108 gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin); in gpio_set_bit()
112 unsigned int pin, uint32_t value) in gpio_set_2bits() argument
114 uint32_t offset = 2 * pin; in gpio_set_2bits()
186 * (in case the pin is in output mode). in test_idr_reset_value()
279 unsigned int pin = test_pin(data); in test_gpio_output_mode() local
286 gpio_set_bit(gpio, ODR, pin, 1); in test_gpio_output_mode()
[all …]
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| /openbmc/u-boot/include/dm/ |
| H A D | pinctrl.h | 13 * struct pinconf_param - pin config parameters
27 * struct pinctrl_ops - pin control operations, to be implemented by
28 * pin controller drivers.
38 * @get_pin_name: return the pin name of the pin selector,
39 * called by the core to figure out which pin it shall do
44 * called by the core to figure out which pin group it shall do
47 * in this driver. (necessary for pin-muxing)
50 * certain device to. (necessary for pin-muxing)
51 * @pinmux_set: enable a certain muxing function with a certain pin.
53 * selects a certain pin to be used. On simple controllers one of them
[all …]
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| /openbmc/u-boot/board/micronas/vct/ |
| H A D | gpio.c | 11 * Find out to which of the 2 gpio modules the pin specified in the
16 #define GPIO_MODULE(pin) ((pin) >> 5) argument
22 #define MASK(pin) (1 << ((pin) & 0x1F)) argument
39 int vct_gpio_dir(int pin, int dir) in vct_gpio_dir() argument
43 gpio_base = BASE_ADDR(GPIO_MODULE(pin)); in vct_gpio_dir()
46 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); in vct_gpio_dir()
48 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); in vct_gpio_dir()
53 void vct_gpio_set(int pin, int val) in vct_gpio_set() argument
57 gpio_base = BASE_ADDR(GPIO_MODULE(pin)); in vct_gpio_set()
60 clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); in vct_gpio_set()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/arm920t/imx/ |
| H A D | generic.c | 20 unsigned int pin = gpio_mode & GPIO_PIN_MASK; in imx_gpio_mode() local
27 PUEN(port) |= (1<<pin); in imx_gpio_mode()
29 PUEN(port) &= ~(1<<pin); in imx_gpio_mode()
33 DDIR(port) |= 1<<pin; in imx_gpio_mode()
35 DDIR(port) &= ~(1<<pin); in imx_gpio_mode()
39 GPR(port) |= (1<<pin); in imx_gpio_mode()
41 GPR(port) &= ~(1<<pin); in imx_gpio_mode()
45 GIUS(port) |= (1<<pin); in imx_gpio_mode()
47 GIUS(port) &= ~(1<<pin); in imx_gpio_mode()
53 if(pin<16) { in imx_gpio_mode()
[all …]
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| /openbmc/u-boot/drivers/pinctrl/exynos/ |
| H A D | pinctrl-exynos.h | 11 #define PIN_CON 0x00 /* Offset of pin function register */
12 #define PIN_DAT 0x04 /* Offset of pin data register */
13 #define PIN_PUD 0x08 /* Offset of pin pull up/down config register */
14 #define PIN_DRV 0x0C /* Offset of pin drive strength register */
17 * struct samsung_pin_bank_data: represent a controller pin-bank data.
18 * @offset: starting offset of the pin-bank registers.
20 * @name: name to be prefixed for each pin in this pin bank.
36 * struct samsung_pin_ctrl: represent a pin controller.
37 * @pin_banks: list of pin banks included in this controller.
38 * @nr_banks: number of pin banks.
[all …]
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| /openbmc/openbmc/meta-ingrasys/meta-zaius/recipes-phosphor/skeleton/obmc-libobmc-intf/ |
| H A D | gpio_defs.json | 19 "pin": "R1", string
24 "pin": "D1", string
29 "pin": "D2", string
34 "pin": "D3", string
39 "pin": "D4", string
44 "pin": "A1", string
49 "pin": "A3", string
54 "pin": "B4", string
59 "pin": "I3", string
64 "pin": "AA0", string
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | pinmux-common.c | 12 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT)) argument
95 #define REG(pin) _R(0x3000 + ((pin) * 4)) argument
97 #define MUX_REG(pin) REG(pin) argument
98 #define MUX_SHIFT(pin) 0 argument
100 #define PULL_REG(pin) REG(pin) argument
101 #define PULL_SHIFT(pin) 2 argument
103 #define TRI_REG(pin) REG(pin) argument
104 #define TRI_SHIFT(pin) 4 argument
157 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) in pinmux_set_func() argument
159 u32 *reg = MUX_REG(pin); in pinmux_set_func()
[all …]
|