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/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip-core.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) in rockchip_verify_config() argument
22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config() local
24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
26 return -EINVAL; in rockchip_verify_config()
29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { in rockchip_verify_config()
30 debug("pin conf pin %d >= %d\n", pin, in rockchip_verify_config()
32 return -EINVAL; in rockchip_verify_config()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/leds/
H A Dkinetic,ktd2692.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markuss Broks <markuss.broks@gmail.com>
13 KTD2692 is the ideal power solution for high-power flash LEDs.
14 It uses ExpressWire single-wire programming for maximum flexibility.
16 The ExpressWire interface through CTRL pin can control LED on/off and
17 enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current,
20 Also, When the AUX pin is pulled high while CTRL pin is high,
21 LED current will be ramped up to the flash-mode current level.
[all …]
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-lpass-lpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
15 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
21 #include "pinctrl-lpass-lpi.h"
29 struct pinctrl_dev *ctrl; member
41 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, in lpi_gpio_read() argument
44 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_read()
47 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, in lpi_gpio_write() argument
50 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); in lpi_gpio_write()
[all …]
H A Dpinctrl-spmi-mpp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
16 #include <linux/pinctrl/pinconf-generic.h>
20 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
23 #include "../pinctrl-utils.h"
28 * Pull Up Values - it indicates whether a pull-up should be
99 /* Qualcomm specific pin configurations */
106 * struct pmic_mpp_pad - keep current MPP settings
109 * @out_value: Cached pin output value.
112 * @paired: Pin operates in paired mode
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
45 /* Magic value to enable writes on jz4780 */
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
80 uint32_t ctrl; in jz4740_rtc_wait_write_ready() local
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
83 ctrl & JZ_RTC_CTRL_WRDY, 0, 1000); in jz4740_rtc_wait_write_ready()
88 uint32_t ctrl; in jz4780_rtc_enable_write() local
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_ptp.c1 // SPDX-License-Identifier: GPL-2.0
26 struct igc_hw *hw = &adapter->hw; in igc_ptp_read()
33 ts->tv_sec = sec; in igc_ptp_read()
34 ts->tv_nsec = nsec; in igc_ptp_read()
40 struct igc_hw *hw = &adapter->hw; in igc_ptp_write_i225()
42 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
43 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
50 struct igc_hw *hw = &igc->hw; in igc_ptp_adjfine_i225()
57 scaled_ppm = -scaled_ppm; in igc_ptp_adjfine_i225()
79 spin_lock_irqsave(&igc->tmreg_lock, flags); in igc_ptp_adjtime_i225()
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/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
31 #include "pinctrl-samsung.h"
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
54 return pmx->nr_groups; in samsung_get_group_count()
62 return pmx->pin_groups[group].name; in samsung_get_group_name()
[all …]
H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
27 * @PINCFG_TYPE_DAT: Pin value configuration.
30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
45 * pin configuration (pull up/down and drive strength) type and its value are
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * Values for the pin CON register, choosing pin function.
65 * enum eint_type - possible external interrupt types.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A Digb_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
38 * +--------------+ +---+---+------+
40 * +--------------+ +---+---+------+
43 * +----------+---+ +--------------+
45 * +----------+---+ +--------------+
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
79 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82576()
96 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82580()
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-synology-ds213j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
30 "marvell,armada-370-xp";
33 stdout-path = "serial0:115200n8";
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
[all …]
/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <asm/mach-types.h>
30 #include <asm/ehci-omap.h>
50 gd->bd->bi_arch_number = MACH_TYPE_DUOVERO; in board_init()
51 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
57 * @brief misc_init_r - Configure board specific configurations
68 /* wifi setup: first enable 32Khz clock from 6030 pmic */ in misc_init_r()
72 printf("Failed to enable 32Khz clock to wifi module\n"); in misc_init_r()
74 /* then setup WIFI_EN as an output pin and send reset pulse */ in misc_init_r()
92 do_set_mux((*ctrl)->control_padconf_core_base, in set_muxconf_regs()
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dkb9202_nand.c1 // SPDX-License-Identifier: GPL-2.0+
18 * hardware specific access to control-lines
33 * Board-specific function to access device control signals
35 static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) in kb9202_nand_hwcontrol() argument
39 if (ctrl & NAND_CTRL_CHANGE) { in kb9202_nand_hwcontrol()
40 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; in kb9202_nand_hwcontrol()
45 if (ctrl & NAND_CLE) in kb9202_nand_hwcontrol()
48 if (ctrl & NAND_ALE) in kb9202_nand_hwcontrol()
51 this->IO_ADDR_W = (void *) IO_ADDR_W; in kb9202_nand_hwcontrol()
53 if (ctrl & NAND_NCE) in kb9202_nand_hwcontrol()
[all …]
/openbmc/linux/drivers/net/phy/
H A Dicplus.c1 // SPDX-License-Identifier: GPL-2.0+
33 /* IP101A/G - IP1001 */
42 #define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */
69 /* The 32-pin IP101GR package can re-configure the mode of the RXER/INTR_32 pin
70 * (pin number 21). The hardware default is RXER (receive error) mode. But it
102 err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c); in ip175c_config_init()
107 err = mdiobus_read(phydev->mdio.bus, 30, 0); in ip175c_config_init()
112 /* enable IP175C mode */ in ip175c_config_init()
113 err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c); in ip175c_config_init()
118 err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420); in ip175c_config_init()
[all …]
H A Dbcm-phy-ptp.c1 // SPDX-License-Identifier: GPL-2.0
16 #include "bcm-phy-lib.h"
134 struct ptp_pin_desc pin; member
158 #define BCM_SKB_CB(skb) ((struct bcm_ptp_skb_cb *)(skb)->cb)
161 #define BCM_MAX_PULSE_8NS ((1U << 9) - 1)
162 #define BCM_MAX_PERIOD_8NS ((1U << 30) - 1)
165 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
192 ts->tv_sec = (hb[3] << 16) | hb[2]; in bcm_ptp_get_framesync_ts()
193 ts->tv_nsec = (hb[1] << 16) | hb[0]; in bcm_ptp_get_framesync_ts()
198 u16 ctrl = orig_ctrl & ~(NSE_FRAMESYNC_MASK | NSE_CAPTURE_EN); in bcm_ptp_framesync_disable() local
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dleon_pci_grpci2.c1 // SPDX-License-Identifier: GPL-2.0
31 * - barcfgs : Custom Configuration of Host's 6 target BARs
32 * - irq_mask : Limit which PCI interrupts are enabled
33 * - do_reset : Force PCI Reset on startup
41 * -1 means not configured (let host driver do default setup).
50 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
65 /* Enable Debugging Configuration Space Access */
72 unsigned int ctrl; /* 0x00 Control */ member
79 unsigned int bars[6]; /* 0x20 read-only PCI BARs */
81 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
[all …]
/openbmc/openbmc/meta-facebook/meta-bletchley/recipes-bletchley/motor-ctrl/files/
H A Dmotor-ctrl1 #!/bin/bash -e
5 # shellcheck source=meta-facebook/meta-bletchley/recipes-bletchley/plat-tools/files/bletchley-commo…
6 source /usr/libexec/bletchley-common-functions
12 # 2. Value of STBY RESET PIN
13 # 3. Value of ENABLE PIN
14 # 4. Value of DIRECTION PIN
15 # 5. Value of Motor Driver VREF PIN
29 echo "Usage: motor-ctrl [sled1 | sled2 | sled3 | sled4 | sled5 | sled6] [f r s]"
35 if [ $# -ne 2 ]; then
40 if [[ "$1" =~ ^(sled[1-6]{1})$ ]]; then
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dsystem_manager_s10.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
17 * Configure all the pin muxes
34 /* Enable the signal for those HPS peripherals that use FPGA. */ in populate_sysmgr_fpgaintf_module()
35 if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
37 if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
39 if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
41 if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
43 writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); in populate_sysmgr_fpgaintf_module()
46 if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
[all …]
/openbmc/linux/drivers/net/hamradio/
H A Dscc.c6 * Please use z8530drv-utils-3.0 with this version.
7 * ------------------
15 * SCC.C - Linux driver for Z8530 based HDLC cards for AX.25 *
28 The code is likely to fail, and so your kernel could --- even
40 For non-Amateur-Radio use please note that you might need a special
60 -------------------------------
62 1994-09-13 started to write the driver, rescued most of my own
71 1995-01-31 changed copyright notice to GPL without limitations.
77 1996-10-05 New semester, new driver...
85 * Invents brand new bugs... ;-)
[all …]
/openbmc/linux/drivers/phy/broadcom/
H A Dphy-brcm-usb-init-synopsys.c1 // SPDX-License-Identifier: GPL-2.0
13 #include "phy-brcm-usb-init.h"
36 /* Register definitions for the USB CTRL block */
101 void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO]; in usb_mdio_write_7211b0()
103 addr &= 0x1f; /* 5-bit address */ in usb_mdio_write_7211b0()
119 void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO]; in usb_mdio_read_7211b0()
121 addr &= 0x1f; /* 5-bit address */ in usb_mdio_read_7211b0()
146 void __iomem *ctrl = params->regs[BRCM_REGS_CTRL]; in xhci_soft_reset() local
147 void __iomem *xhci_gbl = params->regs[BRCM_REGS_XHCI_GBL]; in xhci_soft_reset()
151 USB_CTRL_UNSET(ctrl, USB_PM, XHC_SOFT_RESETB); in xhci_soft_reset()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
40 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
41 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
89 * e1000_set_phy_type - Set the phy type member in the hw struct.
94 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
95 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
97 switch (hw->phy_id) { in e1000_set_phy_type()
103 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
106 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dmxs-auart.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
90 #define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
131 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
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/openbmc/linux/Documentation/core-api/
H A Ddebugging-via-ohci1394.rst2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
28 more common hardware such as x86, x86-64 and PowerPC.
34 Together with a early initialization of the OHCI-1394 controller for debugging,
41 -------
43 The firewire-ohci driver in drivers/firewire uses filtered physical
47 Because the firewire-ohci driver depends on the PCI enumeration to be
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
19 * Pin select: (0) "normal", (1) "dedicate peripheral"
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
49 * @bank_read: Read a bank setting as a single 32-bit value
50 * @bank_write: Write a bank setting as a single 32-bit value
53 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55 * a value from (to) these registers. The IMR register consists of four 16-bit
56 * port values, packed into two 32-bit registers. Use @imr_line_pos to get the
57 * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than
[all …]

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