1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
25d07b786SDaniel Hellstrom /*
35d07b786SDaniel Hellstrom * leon_pci_grpci2.c: GRPCI2 Host PCI driver
45d07b786SDaniel Hellstrom *
55d07b786SDaniel Hellstrom * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
65d07b786SDaniel Hellstrom *
75d07b786SDaniel Hellstrom */
85d07b786SDaniel Hellstrom
95d07b786SDaniel Hellstrom #include <linux/kernel.h>
105d07b786SDaniel Hellstrom #include <linux/pci.h>
11d6250ee2SPaul Gortmaker #include <linux/slab.h>
125d07b786SDaniel Hellstrom #include <linux/delay.h>
13066bcacaSPaul Gortmaker #include <linux/export.h>
14263291faSRob Herring #include <linux/of.h>
15263291faSRob Herring #include <linux/platform_device.h>
16263291faSRob Herring
175d07b786SDaniel Hellstrom #include <asm/io.h>
185d07b786SDaniel Hellstrom #include <asm/leon.h>
195d07b786SDaniel Hellstrom #include <asm/vaddrs.h>
205d07b786SDaniel Hellstrom #include <asm/sections.h>
215d07b786SDaniel Hellstrom #include <asm/leon_pci.h>
225d07b786SDaniel Hellstrom
235d07b786SDaniel Hellstrom #include "irq.h"
245d07b786SDaniel Hellstrom
255d07b786SDaniel Hellstrom struct grpci2_barcfg {
265d07b786SDaniel Hellstrom unsigned long pciadr; /* PCI Space Address */
275d07b786SDaniel Hellstrom unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
285d07b786SDaniel Hellstrom };
295d07b786SDaniel Hellstrom
305d07b786SDaniel Hellstrom /* Device Node Configuration options:
315d07b786SDaniel Hellstrom * - barcfgs : Custom Configuration of Host's 6 target BARs
325d07b786SDaniel Hellstrom * - irq_mask : Limit which PCI interrupts are enabled
335d07b786SDaniel Hellstrom * - do_reset : Force PCI Reset on startup
345d07b786SDaniel Hellstrom *
355d07b786SDaniel Hellstrom * barcfgs
365d07b786SDaniel Hellstrom * =======
375d07b786SDaniel Hellstrom *
385d07b786SDaniel Hellstrom * Optional custom Target BAR configuration (see struct grpci2_barcfg). All
395d07b786SDaniel Hellstrom * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
405d07b786SDaniel Hellstrom *
415d07b786SDaniel Hellstrom * -1 means not configured (let host driver do default setup).
425d07b786SDaniel Hellstrom *
435d07b786SDaniel Hellstrom * [i*2+0] = PCI Address of BAR[i] on target interface
445d07b786SDaniel Hellstrom * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
455d07b786SDaniel Hellstrom *
465d07b786SDaniel Hellstrom *
475d07b786SDaniel Hellstrom * irq_mask
485d07b786SDaniel Hellstrom * ========
495d07b786SDaniel Hellstrom *
505d07b786SDaniel Hellstrom * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
515d07b786SDaniel Hellstrom * all are enabled. Use this when PCI interrupt pins are floating on PCB.
525d07b786SDaniel Hellstrom * int, len=4.
535d07b786SDaniel Hellstrom * bit0 = PCI INTA#
545d07b786SDaniel Hellstrom * bit1 = PCI INTB#
555d07b786SDaniel Hellstrom * bit2 = PCI INTC#
565d07b786SDaniel Hellstrom * bit3 = PCI INTD#
575d07b786SDaniel Hellstrom *
585d07b786SDaniel Hellstrom *
595d07b786SDaniel Hellstrom * reset
605d07b786SDaniel Hellstrom * =====
615d07b786SDaniel Hellstrom *
625d07b786SDaniel Hellstrom * Force PCI reset on startup. int, len=4
635d07b786SDaniel Hellstrom */
645d07b786SDaniel Hellstrom
655d07b786SDaniel Hellstrom /* Enable Debugging Configuration Space Access */
665d07b786SDaniel Hellstrom #undef GRPCI2_DEBUG_CFGACCESS
675d07b786SDaniel Hellstrom
685d07b786SDaniel Hellstrom /*
695d07b786SDaniel Hellstrom * GRPCI2 APB Register MAP
705d07b786SDaniel Hellstrom */
715d07b786SDaniel Hellstrom struct grpci2_regs {
725d07b786SDaniel Hellstrom unsigned int ctrl; /* 0x00 Control */
735d07b786SDaniel Hellstrom unsigned int sts_cap; /* 0x04 Status / Capabilities */
745d07b786SDaniel Hellstrom int res1; /* 0x08 */
755d07b786SDaniel Hellstrom unsigned int io_map; /* 0x0C I/O Map address */
765d07b786SDaniel Hellstrom unsigned int dma_ctrl; /* 0x10 DMA */
775d07b786SDaniel Hellstrom unsigned int dma_bdbase; /* 0x14 DMA */
785d07b786SDaniel Hellstrom int res2[2]; /* 0x18 */
795d07b786SDaniel Hellstrom unsigned int bars[6]; /* 0x20 read-only PCI BARs */
805d07b786SDaniel Hellstrom int res3[2]; /* 0x38 */
815d07b786SDaniel Hellstrom unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
825d07b786SDaniel Hellstrom
835d07b786SDaniel Hellstrom /* PCI Trace Buffer Registers (OPTIONAL) */
845d07b786SDaniel Hellstrom unsigned int t_ctrl; /* 0x80 */
855d07b786SDaniel Hellstrom unsigned int t_cnt; /* 0x84 */
865d07b786SDaniel Hellstrom unsigned int t_adpat; /* 0x88 */
875d07b786SDaniel Hellstrom unsigned int t_admask; /* 0x8C */
885d07b786SDaniel Hellstrom unsigned int t_sigpat; /* 0x90 */
895d07b786SDaniel Hellstrom unsigned int t_sigmask; /* 0x94 */
905d07b786SDaniel Hellstrom unsigned int t_adstate; /* 0x98 */
915d07b786SDaniel Hellstrom unsigned int t_sigstate; /* 0x9C */
925d07b786SDaniel Hellstrom };
935d07b786SDaniel Hellstrom
945d07b786SDaniel Hellstrom #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
955d07b786SDaniel Hellstrom #define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
965d07b786SDaniel Hellstrom
975d07b786SDaniel Hellstrom #define CTRL_BUS_BIT 16
985d07b786SDaniel Hellstrom
995d07b786SDaniel Hellstrom #define CTRL_RESET (1<<31)
1005d07b786SDaniel Hellstrom #define CTRL_SI (1<<27)
1015d07b786SDaniel Hellstrom #define CTRL_PE (1<<26)
1025d07b786SDaniel Hellstrom #define CTRL_EI (1<<25)
1035d07b786SDaniel Hellstrom #define CTRL_ER (1<<24)
1045d07b786SDaniel Hellstrom #define CTRL_BUS (0xff<<CTRL_BUS_BIT)
1055d07b786SDaniel Hellstrom #define CTRL_HOSTINT 0xf
1065d07b786SDaniel Hellstrom
1075d07b786SDaniel Hellstrom #define STS_HOST_BIT 31
1085d07b786SDaniel Hellstrom #define STS_MST_BIT 30
1095d07b786SDaniel Hellstrom #define STS_TAR_BIT 29
1105d07b786SDaniel Hellstrom #define STS_DMA_BIT 28
1115d07b786SDaniel Hellstrom #define STS_DI_BIT 27
1125d07b786SDaniel Hellstrom #define STS_HI_BIT 26
1135d07b786SDaniel Hellstrom #define STS_IRQMODE_BIT 24
1145d07b786SDaniel Hellstrom #define STS_TRACE_BIT 23
1155d07b786SDaniel Hellstrom #define STS_CFGERRVALID_BIT 20
1165d07b786SDaniel Hellstrom #define STS_CFGERR_BIT 19
1175d07b786SDaniel Hellstrom #define STS_INTTYPE_BIT 12
1185d07b786SDaniel Hellstrom #define STS_INTSTS_BIT 8
1195d07b786SDaniel Hellstrom #define STS_FDEPTH_BIT 2
1205d07b786SDaniel Hellstrom #define STS_FNUM_BIT 0
1215d07b786SDaniel Hellstrom
1225d07b786SDaniel Hellstrom #define STS_HOST (1<<STS_HOST_BIT)
1235d07b786SDaniel Hellstrom #define STS_MST (1<<STS_MST_BIT)
1245d07b786SDaniel Hellstrom #define STS_TAR (1<<STS_TAR_BIT)
1255d07b786SDaniel Hellstrom #define STS_DMA (1<<STS_DMA_BIT)
1265d07b786SDaniel Hellstrom #define STS_DI (1<<STS_DI_BIT)
1275d07b786SDaniel Hellstrom #define STS_HI (1<<STS_HI_BIT)
1285d07b786SDaniel Hellstrom #define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
1295d07b786SDaniel Hellstrom #define STS_TRACE (1<<STS_TRACE_BIT)
1305d07b786SDaniel Hellstrom #define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
1315d07b786SDaniel Hellstrom #define STS_CFGERR (1<<STS_CFGERR_BIT)
1325d07b786SDaniel Hellstrom #define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
1335d07b786SDaniel Hellstrom #define STS_INTSTS (0xf<<STS_INTSTS_BIT)
1345d07b786SDaniel Hellstrom #define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
1355d07b786SDaniel Hellstrom #define STS_FNUM (0x3<<STS_FNUM_BIT)
1365d07b786SDaniel Hellstrom
1375d07b786SDaniel Hellstrom #define STS_ISYSERR (1<<17)
1385d07b786SDaniel Hellstrom #define STS_IDMA (1<<16)
1395d07b786SDaniel Hellstrom #define STS_IDMAERR (1<<15)
1405d07b786SDaniel Hellstrom #define STS_IMSTABRT (1<<14)
1415d07b786SDaniel Hellstrom #define STS_ITGTABRT (1<<13)
1425d07b786SDaniel Hellstrom #define STS_IPARERR (1<<12)
1435d07b786SDaniel Hellstrom
1445d07b786SDaniel Hellstrom #define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
1455d07b786SDaniel Hellstrom
1465d07b786SDaniel Hellstrom struct grpci2_bd_chan {
1475d07b786SDaniel Hellstrom unsigned int ctrl; /* 0x00 DMA Control */
1485d07b786SDaniel Hellstrom unsigned int nchan; /* 0x04 Next DMA Channel Address */
1495d07b786SDaniel Hellstrom unsigned int nbd; /* 0x08 Next Data Descriptor in chan */
1505d07b786SDaniel Hellstrom unsigned int res; /* 0x0C Reserved */
1515d07b786SDaniel Hellstrom };
1525d07b786SDaniel Hellstrom
1535d07b786SDaniel Hellstrom #define BD_CHAN_EN 0x80000000
1545d07b786SDaniel Hellstrom #define BD_CHAN_TYPE 0x00300000
1555d07b786SDaniel Hellstrom #define BD_CHAN_BDCNT 0x0000ffff
1565d07b786SDaniel Hellstrom #define BD_CHAN_EN_BIT 31
1575d07b786SDaniel Hellstrom #define BD_CHAN_TYPE_BIT 20
1585d07b786SDaniel Hellstrom #define BD_CHAN_BDCNT_BIT 0
1595d07b786SDaniel Hellstrom
1605d07b786SDaniel Hellstrom struct grpci2_bd_data {
1615d07b786SDaniel Hellstrom unsigned int ctrl; /* 0x00 DMA Data Control */
1625d07b786SDaniel Hellstrom unsigned int pci_adr; /* 0x04 PCI Start Address */
1635d07b786SDaniel Hellstrom unsigned int ahb_adr; /* 0x08 AHB Start address */
1645d07b786SDaniel Hellstrom unsigned int next; /* 0x0C Next Data Descriptor in chan */
1655d07b786SDaniel Hellstrom };
1665d07b786SDaniel Hellstrom
1675d07b786SDaniel Hellstrom #define BD_DATA_EN 0x80000000
1685d07b786SDaniel Hellstrom #define BD_DATA_IE 0x40000000
1695d07b786SDaniel Hellstrom #define BD_DATA_DR 0x20000000
1705d07b786SDaniel Hellstrom #define BD_DATA_TYPE 0x00300000
1715d07b786SDaniel Hellstrom #define BD_DATA_ER 0x00080000
1725d07b786SDaniel Hellstrom #define BD_DATA_LEN 0x0000ffff
1735d07b786SDaniel Hellstrom #define BD_DATA_EN_BIT 31
1745d07b786SDaniel Hellstrom #define BD_DATA_IE_BIT 30
1755d07b786SDaniel Hellstrom #define BD_DATA_DR_BIT 29
1765d07b786SDaniel Hellstrom #define BD_DATA_TYPE_BIT 20
1775d07b786SDaniel Hellstrom #define BD_DATA_ER_BIT 19
1785d07b786SDaniel Hellstrom #define BD_DATA_LEN_BIT 0
1795d07b786SDaniel Hellstrom
1805d07b786SDaniel Hellstrom /* GRPCI2 Capability */
1815d07b786SDaniel Hellstrom struct grpci2_cap_first {
1825d07b786SDaniel Hellstrom unsigned int ctrl;
1835d07b786SDaniel Hellstrom unsigned int pci2ahb_map[6];
1845d07b786SDaniel Hellstrom unsigned int ext2ahb_map;
1855d07b786SDaniel Hellstrom unsigned int io_map;
1865d07b786SDaniel Hellstrom unsigned int pcibar_size[6];
1875d07b786SDaniel Hellstrom };
1885d07b786SDaniel Hellstrom #define CAP9_CTRL_OFS 0
1895d07b786SDaniel Hellstrom #define CAP9_BAR_OFS 0x4
1905d07b786SDaniel Hellstrom #define CAP9_IOMAP_OFS 0x20
1915d07b786SDaniel Hellstrom #define CAP9_BARSIZE_OFS 0x24
1925d07b786SDaniel Hellstrom
193a2956428SDaniel Hellstrom #define TGT 256
194a2956428SDaniel Hellstrom
1955d07b786SDaniel Hellstrom struct grpci2_priv {
1965d07b786SDaniel Hellstrom struct leon_pci_info info; /* must be on top of this structure */
1973731e199SSam Ravnborg struct grpci2_regs __iomem *regs;
1985d07b786SDaniel Hellstrom char irq;
1995d07b786SDaniel Hellstrom char irq_mode; /* IRQ Mode from CAPSTS REG */
2005d07b786SDaniel Hellstrom char bt_enabled;
2015d07b786SDaniel Hellstrom char do_reset;
2025d07b786SDaniel Hellstrom char irq_mask;
2035d07b786SDaniel Hellstrom u32 pciid; /* PCI ID of Host */
2045d07b786SDaniel Hellstrom unsigned char irq_map[4];
2055d07b786SDaniel Hellstrom
2065d07b786SDaniel Hellstrom /* Virtual IRQ numbers */
2075d07b786SDaniel Hellstrom unsigned int virq_err;
2085d07b786SDaniel Hellstrom unsigned int virq_dma;
2095d07b786SDaniel Hellstrom
2105d07b786SDaniel Hellstrom /* AHB PCI Windows */
2115d07b786SDaniel Hellstrom unsigned long pci_area; /* MEMORY */
2125d07b786SDaniel Hellstrom unsigned long pci_area_end;
2135d07b786SDaniel Hellstrom unsigned long pci_io; /* I/O */
2145d07b786SDaniel Hellstrom unsigned long pci_conf; /* CONFIGURATION */
2155d07b786SDaniel Hellstrom unsigned long pci_conf_end;
2165d07b786SDaniel Hellstrom unsigned long pci_io_va;
2175d07b786SDaniel Hellstrom
2185d07b786SDaniel Hellstrom struct grpci2_barcfg tgtbars[6];
2195d07b786SDaniel Hellstrom };
2205d07b786SDaniel Hellstrom
2213731e199SSam Ravnborg static DEFINE_SPINLOCK(grpci2_dev_lock);
2223731e199SSam Ravnborg static struct grpci2_priv *grpci2priv;
2235d07b786SDaniel Hellstrom
grpci2_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)2243731e199SSam Ravnborg static int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
2255d07b786SDaniel Hellstrom {
2265d07b786SDaniel Hellstrom struct grpci2_priv *priv = dev->bus->sysdata;
2275d07b786SDaniel Hellstrom int irq_group;
2285d07b786SDaniel Hellstrom
2295d07b786SDaniel Hellstrom /* Use default IRQ decoding on PCI BUS0 according slot numbering */
2305d07b786SDaniel Hellstrom irq_group = slot & 0x3;
2315d07b786SDaniel Hellstrom pin = ((pin - 1) + irq_group) & 0x3;
2325d07b786SDaniel Hellstrom
2335d07b786SDaniel Hellstrom return priv->irq_map[pin];
2345d07b786SDaniel Hellstrom }
2355d07b786SDaniel Hellstrom
grpci2_cfg_r32(struct grpci2_priv * priv,unsigned int bus,unsigned int devfn,int where,u32 * val)2365d07b786SDaniel Hellstrom static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
2375d07b786SDaniel Hellstrom unsigned int devfn, int where, u32 *val)
2385d07b786SDaniel Hellstrom {
2395d07b786SDaniel Hellstrom unsigned int *pci_conf;
2405d07b786SDaniel Hellstrom unsigned long flags;
2415d07b786SDaniel Hellstrom u32 tmp;
2425d07b786SDaniel Hellstrom
2435d07b786SDaniel Hellstrom if (where & 0x3)
2445d07b786SDaniel Hellstrom return -EINVAL;
2455d07b786SDaniel Hellstrom
246a2956428SDaniel Hellstrom if (bus == 0) {
247a2956428SDaniel Hellstrom devfn += (0x8 * 6); /* start at AD16=Device0 */
248a2956428SDaniel Hellstrom } else if (bus == TGT) {
249a2956428SDaniel Hellstrom bus = 0;
250a2956428SDaniel Hellstrom devfn = 0; /* special case: bridge controller itself */
251a2956428SDaniel Hellstrom }
2525d07b786SDaniel Hellstrom
2535d07b786SDaniel Hellstrom /* Select bus */
2545d07b786SDaniel Hellstrom spin_lock_irqsave(&grpci2_dev_lock, flags);
2555d07b786SDaniel Hellstrom REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
2565d07b786SDaniel Hellstrom (bus << 16));
2575d07b786SDaniel Hellstrom spin_unlock_irqrestore(&grpci2_dev_lock, flags);
2585d07b786SDaniel Hellstrom
2595d07b786SDaniel Hellstrom /* clear old status */
2605d07b786SDaniel Hellstrom REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
2615d07b786SDaniel Hellstrom
2625d07b786SDaniel Hellstrom pci_conf = (unsigned int *) (priv->pci_conf |
2635d07b786SDaniel Hellstrom (devfn << 8) | (where & 0xfc));
2645d07b786SDaniel Hellstrom tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
2655d07b786SDaniel Hellstrom
2665d07b786SDaniel Hellstrom /* Wait until GRPCI2 signals that CFG access is done, it should be
2675d07b786SDaniel Hellstrom * done instantaneously unless a DMA operation is ongoing...
2685d07b786SDaniel Hellstrom */
2695d07b786SDaniel Hellstrom while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
2705d07b786SDaniel Hellstrom ;
2715d07b786SDaniel Hellstrom
2725d07b786SDaniel Hellstrom if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
2735d07b786SDaniel Hellstrom *val = 0xffffffff;
2745d07b786SDaniel Hellstrom } else {
2755d07b786SDaniel Hellstrom /* Bus always little endian (unaffected by byte-swapping) */
27601c6505dSSam Ravnborg *val = swab32(tmp);
2775d07b786SDaniel Hellstrom }
2785d07b786SDaniel Hellstrom
2795d07b786SDaniel Hellstrom return 0;
2805d07b786SDaniel Hellstrom }
2815d07b786SDaniel Hellstrom
grpci2_cfg_r16(struct grpci2_priv * priv,unsigned int bus,unsigned int devfn,int where,u32 * val)2825d07b786SDaniel Hellstrom static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
2835d07b786SDaniel Hellstrom unsigned int devfn, int where, u32 *val)
2845d07b786SDaniel Hellstrom {
2855d07b786SDaniel Hellstrom u32 v;
2865d07b786SDaniel Hellstrom int ret;
2875d07b786SDaniel Hellstrom
2885d07b786SDaniel Hellstrom if (where & 0x1)
2895d07b786SDaniel Hellstrom return -EINVAL;
2905d07b786SDaniel Hellstrom ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
2915d07b786SDaniel Hellstrom *val = 0xffff & (v >> (8 * (where & 0x3)));
2925d07b786SDaniel Hellstrom return ret;
2935d07b786SDaniel Hellstrom }
2945d07b786SDaniel Hellstrom
grpci2_cfg_r8(struct grpci2_priv * priv,unsigned int bus,unsigned int devfn,int where,u32 * val)2955d07b786SDaniel Hellstrom static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
2965d07b786SDaniel Hellstrom unsigned int devfn, int where, u32 *val)
2975d07b786SDaniel Hellstrom {
2985d07b786SDaniel Hellstrom u32 v;
2995d07b786SDaniel Hellstrom int ret;
3005d07b786SDaniel Hellstrom
3015d07b786SDaniel Hellstrom ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
3025d07b786SDaniel Hellstrom *val = 0xff & (v >> (8 * (where & 3)));
3035d07b786SDaniel Hellstrom
3045d07b786SDaniel Hellstrom return ret;
3055d07b786SDaniel Hellstrom }
3065d07b786SDaniel Hellstrom
grpci2_cfg_w32(struct grpci2_priv * priv,unsigned int bus,unsigned int devfn,int where,u32 val)3075d07b786SDaniel Hellstrom static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
3085d07b786SDaniel Hellstrom unsigned int devfn, int where, u32 val)
3095d07b786SDaniel Hellstrom {
3105d07b786SDaniel Hellstrom unsigned int *pci_conf;
3115d07b786SDaniel Hellstrom unsigned long flags;
3125d07b786SDaniel Hellstrom
3135d07b786SDaniel Hellstrom if (where & 0x3)
3145d07b786SDaniel Hellstrom return -EINVAL;
3155d07b786SDaniel Hellstrom
316a2956428SDaniel Hellstrom if (bus == 0) {
317a2956428SDaniel Hellstrom devfn += (0x8 * 6); /* start at AD16=Device0 */
318a2956428SDaniel Hellstrom } else if (bus == TGT) {
319a2956428SDaniel Hellstrom bus = 0;
320a2956428SDaniel Hellstrom devfn = 0; /* special case: bridge controller itself */
321a2956428SDaniel Hellstrom }
3225d07b786SDaniel Hellstrom
3235d07b786SDaniel Hellstrom /* Select bus */
3245d07b786SDaniel Hellstrom spin_lock_irqsave(&grpci2_dev_lock, flags);
3255d07b786SDaniel Hellstrom REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
3265d07b786SDaniel Hellstrom (bus << 16));
3275d07b786SDaniel Hellstrom spin_unlock_irqrestore(&grpci2_dev_lock, flags);
3285d07b786SDaniel Hellstrom
3295d07b786SDaniel Hellstrom /* clear old status */
3305d07b786SDaniel Hellstrom REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
3315d07b786SDaniel Hellstrom
3325d07b786SDaniel Hellstrom pci_conf = (unsigned int *) (priv->pci_conf |
3335d07b786SDaniel Hellstrom (devfn << 8) | (where & 0xfc));
33401c6505dSSam Ravnborg LEON3_BYPASS_STORE_PA(pci_conf, swab32(val));
3355d07b786SDaniel Hellstrom
3365d07b786SDaniel Hellstrom /* Wait until GRPCI2 signals that CFG access is done, it should be
3375d07b786SDaniel Hellstrom * done instantaneously unless a DMA operation is ongoing...
3385d07b786SDaniel Hellstrom */
3395d07b786SDaniel Hellstrom while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
3405d07b786SDaniel Hellstrom ;
3415d07b786SDaniel Hellstrom
3425d07b786SDaniel Hellstrom return 0;
3435d07b786SDaniel Hellstrom }
3445d07b786SDaniel Hellstrom
grpci2_cfg_w16(struct grpci2_priv * priv,unsigned int bus,unsigned int devfn,int where,u32 val)3455d07b786SDaniel Hellstrom static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
3465d07b786SDaniel Hellstrom unsigned int devfn, int where, u32 val)
3475d07b786SDaniel Hellstrom {
3485d07b786SDaniel Hellstrom int ret;
3495d07b786SDaniel Hellstrom u32 v;
3505d07b786SDaniel Hellstrom
3515d07b786SDaniel Hellstrom if (where & 0x1)
3525d07b786SDaniel Hellstrom return -EINVAL;
3535d07b786SDaniel Hellstrom ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
3545d07b786SDaniel Hellstrom if (ret)
3555d07b786SDaniel Hellstrom return ret;
3565d07b786SDaniel Hellstrom v = (v & ~(0xffff << (8 * (where & 0x3)))) |
3575d07b786SDaniel Hellstrom ((0xffff & val) << (8 * (where & 0x3)));
3585d07b786SDaniel Hellstrom return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
3595d07b786SDaniel Hellstrom }
3605d07b786SDaniel Hellstrom
grpci2_cfg_w8(struct grpci2_priv * priv,unsigned int bus,unsigned int devfn,int where,u32 val)3615d07b786SDaniel Hellstrom static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
3625d07b786SDaniel Hellstrom unsigned int devfn, int where, u32 val)
3635d07b786SDaniel Hellstrom {
3645d07b786SDaniel Hellstrom int ret;
3655d07b786SDaniel Hellstrom u32 v;
3665d07b786SDaniel Hellstrom
3675d07b786SDaniel Hellstrom ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
3685d07b786SDaniel Hellstrom if (ret != 0)
3695d07b786SDaniel Hellstrom return ret;
3705d07b786SDaniel Hellstrom v = (v & ~(0xff << (8 * (where & 0x3)))) |
3715d07b786SDaniel Hellstrom ((0xff & val) << (8 * (where & 0x3)));
3725d07b786SDaniel Hellstrom return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
3735d07b786SDaniel Hellstrom }
3745d07b786SDaniel Hellstrom
3755d07b786SDaniel Hellstrom /* Read from Configuration Space. When entering here the PCI layer has taken
3765d07b786SDaniel Hellstrom * the pci_lock spinlock and IRQ is off.
3775d07b786SDaniel Hellstrom */
grpci2_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)3785d07b786SDaniel Hellstrom static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
3795d07b786SDaniel Hellstrom int where, int size, u32 *val)
3805d07b786SDaniel Hellstrom {
3815d07b786SDaniel Hellstrom struct grpci2_priv *priv = grpci2priv;
3825d07b786SDaniel Hellstrom unsigned int busno = bus->number;
3835d07b786SDaniel Hellstrom int ret;
3845d07b786SDaniel Hellstrom
385a2956428SDaniel Hellstrom if (PCI_SLOT(devfn) > 15 || busno > 255) {
3865d07b786SDaniel Hellstrom *val = ~0;
3875d07b786SDaniel Hellstrom return 0;
3885d07b786SDaniel Hellstrom }
3895d07b786SDaniel Hellstrom
3905d07b786SDaniel Hellstrom switch (size) {
3915d07b786SDaniel Hellstrom case 1:
3925d07b786SDaniel Hellstrom ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
3935d07b786SDaniel Hellstrom break;
3945d07b786SDaniel Hellstrom case 2:
3955d07b786SDaniel Hellstrom ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
3965d07b786SDaniel Hellstrom break;
3975d07b786SDaniel Hellstrom case 4:
3985d07b786SDaniel Hellstrom ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
3995d07b786SDaniel Hellstrom break;
4005d07b786SDaniel Hellstrom default:
4015d07b786SDaniel Hellstrom ret = -EINVAL;
4025d07b786SDaniel Hellstrom break;
4035d07b786SDaniel Hellstrom }
4045d07b786SDaniel Hellstrom
4055d07b786SDaniel Hellstrom #ifdef GRPCI2_DEBUG_CFGACCESS
4065d07b786SDaniel Hellstrom printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
4075d07b786SDaniel Hellstrom "size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
4085d07b786SDaniel Hellstrom *val, size);
4095d07b786SDaniel Hellstrom #endif
4105d07b786SDaniel Hellstrom
4115d07b786SDaniel Hellstrom return ret;
4125d07b786SDaniel Hellstrom }
4135d07b786SDaniel Hellstrom
4145d07b786SDaniel Hellstrom /* Write to Configuration Space. When entering here the PCI layer has taken
4155d07b786SDaniel Hellstrom * the pci_lock spinlock and IRQ is off.
4165d07b786SDaniel Hellstrom */
grpci2_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)4175d07b786SDaniel Hellstrom static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
4185d07b786SDaniel Hellstrom int where, int size, u32 val)
4195d07b786SDaniel Hellstrom {
4205d07b786SDaniel Hellstrom struct grpci2_priv *priv = grpci2priv;
4215d07b786SDaniel Hellstrom unsigned int busno = bus->number;
4225d07b786SDaniel Hellstrom
423a2956428SDaniel Hellstrom if (PCI_SLOT(devfn) > 15 || busno > 255)
4245d07b786SDaniel Hellstrom return 0;
4255d07b786SDaniel Hellstrom
4265d07b786SDaniel Hellstrom #ifdef GRPCI2_DEBUG_CFGACCESS
4275d07b786SDaniel Hellstrom printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
4285d07b786SDaniel Hellstrom "val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
4295d07b786SDaniel Hellstrom where, size, val);
4305d07b786SDaniel Hellstrom #endif
4315d07b786SDaniel Hellstrom
4325d07b786SDaniel Hellstrom switch (size) {
4335d07b786SDaniel Hellstrom default:
4345d07b786SDaniel Hellstrom return -EINVAL;
4355d07b786SDaniel Hellstrom case 1:
4365d07b786SDaniel Hellstrom return grpci2_cfg_w8(priv, busno, devfn, where, val);
4375d07b786SDaniel Hellstrom case 2:
4385d07b786SDaniel Hellstrom return grpci2_cfg_w16(priv, busno, devfn, where, val);
4395d07b786SDaniel Hellstrom case 4:
4405d07b786SDaniel Hellstrom return grpci2_cfg_w32(priv, busno, devfn, where, val);
4415d07b786SDaniel Hellstrom }
4425d07b786SDaniel Hellstrom }
4435d07b786SDaniel Hellstrom
4445d07b786SDaniel Hellstrom static struct pci_ops grpci2_ops = {
4455d07b786SDaniel Hellstrom .read = grpci2_read_config,
4465d07b786SDaniel Hellstrom .write = grpci2_write_config,
4475d07b786SDaniel Hellstrom };
4485d07b786SDaniel Hellstrom
4495d07b786SDaniel Hellstrom /* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
4505d07b786SDaniel Hellstrom * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
4515d07b786SDaniel Hellstrom * this is not needed and the standard IRQ controller can be used.
4525d07b786SDaniel Hellstrom */
4535d07b786SDaniel Hellstrom
grpci2_mask_irq(struct irq_data * data)4545d07b786SDaniel Hellstrom static void grpci2_mask_irq(struct irq_data *data)
4555d07b786SDaniel Hellstrom {
4565d07b786SDaniel Hellstrom unsigned long flags;
4575d07b786SDaniel Hellstrom unsigned int irqidx;
4585d07b786SDaniel Hellstrom struct grpci2_priv *priv = grpci2priv;
4595d07b786SDaniel Hellstrom
4605d07b786SDaniel Hellstrom irqidx = (unsigned int)data->chip_data - 1;
4615d07b786SDaniel Hellstrom if (irqidx > 3) /* only mask PCI interrupts here */
4625d07b786SDaniel Hellstrom return;
4635d07b786SDaniel Hellstrom
4645d07b786SDaniel Hellstrom spin_lock_irqsave(&grpci2_dev_lock, flags);
4655d07b786SDaniel Hellstrom REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
4665d07b786SDaniel Hellstrom spin_unlock_irqrestore(&grpci2_dev_lock, flags);
4675d07b786SDaniel Hellstrom }
4685d07b786SDaniel Hellstrom
grpci2_unmask_irq(struct irq_data * data)4695d07b786SDaniel Hellstrom static void grpci2_unmask_irq(struct irq_data *data)
4705d07b786SDaniel Hellstrom {
4715d07b786SDaniel Hellstrom unsigned long flags;
4725d07b786SDaniel Hellstrom unsigned int irqidx;
4735d07b786SDaniel Hellstrom struct grpci2_priv *priv = grpci2priv;
4745d07b786SDaniel Hellstrom
4755d07b786SDaniel Hellstrom irqidx = (unsigned int)data->chip_data - 1;
4765d07b786SDaniel Hellstrom if (irqidx > 3) /* only unmask PCI interrupts here */
4775d07b786SDaniel Hellstrom return;
4785d07b786SDaniel Hellstrom
4795d07b786SDaniel Hellstrom spin_lock_irqsave(&grpci2_dev_lock, flags);
4805d07b786SDaniel Hellstrom REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
4815d07b786SDaniel Hellstrom spin_unlock_irqrestore(&grpci2_dev_lock, flags);
4825d07b786SDaniel Hellstrom }
4835d07b786SDaniel Hellstrom
grpci2_startup_irq(struct irq_data * data)4845d07b786SDaniel Hellstrom static unsigned int grpci2_startup_irq(struct irq_data *data)
4855d07b786SDaniel Hellstrom {
4865d07b786SDaniel Hellstrom grpci2_unmask_irq(data);
4875d07b786SDaniel Hellstrom return 0;
4885d07b786SDaniel Hellstrom }
4895d07b786SDaniel Hellstrom
grpci2_shutdown_irq(struct irq_data * data)4905d07b786SDaniel Hellstrom static void grpci2_shutdown_irq(struct irq_data *data)
4915d07b786SDaniel Hellstrom {
4925d07b786SDaniel Hellstrom grpci2_mask_irq(data);
4935d07b786SDaniel Hellstrom }
4945d07b786SDaniel Hellstrom
4955d07b786SDaniel Hellstrom static struct irq_chip grpci2_irq = {
4965d07b786SDaniel Hellstrom .name = "grpci2",
4975d07b786SDaniel Hellstrom .irq_startup = grpci2_startup_irq,
4985d07b786SDaniel Hellstrom .irq_shutdown = grpci2_shutdown_irq,
4995d07b786SDaniel Hellstrom .irq_mask = grpci2_mask_irq,
5005d07b786SDaniel Hellstrom .irq_unmask = grpci2_unmask_irq,
5015d07b786SDaniel Hellstrom };
5025d07b786SDaniel Hellstrom
5035d07b786SDaniel Hellstrom /* Handle one or multiple IRQs from the PCI core */
grpci2_pci_flow_irq(struct irq_desc * desc)504bd0b9ac4SThomas Gleixner static void grpci2_pci_flow_irq(struct irq_desc *desc)
5055d07b786SDaniel Hellstrom {
5065d07b786SDaniel Hellstrom struct grpci2_priv *priv = grpci2priv;
5075d07b786SDaniel Hellstrom int i, ack = 0;
5085d07b786SDaniel Hellstrom unsigned int ctrl, sts_cap, pci_ints;
5095d07b786SDaniel Hellstrom
5105d07b786SDaniel Hellstrom ctrl = REGLOAD(priv->regs->ctrl);
5115d07b786SDaniel Hellstrom sts_cap = REGLOAD(priv->regs->sts_cap);
5125d07b786SDaniel Hellstrom
5135d07b786SDaniel Hellstrom /* Error Interrupt? */
5145d07b786SDaniel Hellstrom if (sts_cap & STS_ERR_IRQ) {
5155d07b786SDaniel Hellstrom generic_handle_irq(priv->virq_err);
5165d07b786SDaniel Hellstrom ack = 1;
5175d07b786SDaniel Hellstrom }
5185d07b786SDaniel Hellstrom
5195d07b786SDaniel Hellstrom /* PCI Interrupt? */
5205d07b786SDaniel Hellstrom pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
5215d07b786SDaniel Hellstrom if (pci_ints) {
5225d07b786SDaniel Hellstrom /* Call respective PCI Interrupt handler */
5235d07b786SDaniel Hellstrom for (i = 0; i < 4; i++) {
5245d07b786SDaniel Hellstrom if (pci_ints & (1 << i))
5255d07b786SDaniel Hellstrom generic_handle_irq(priv->irq_map[i]);
5265d07b786SDaniel Hellstrom }
5275d07b786SDaniel Hellstrom ack = 1;
5285d07b786SDaniel Hellstrom }
5295d07b786SDaniel Hellstrom
5305d07b786SDaniel Hellstrom /*
5315d07b786SDaniel Hellstrom * Decode DMA Interrupt only when shared with Err and PCI INTX#, when
5325d07b786SDaniel Hellstrom * the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
5335d07b786SDaniel Hellstrom * goes directly to DMA ISR.
5345d07b786SDaniel Hellstrom */
5355d07b786SDaniel Hellstrom if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
5365d07b786SDaniel Hellstrom generic_handle_irq(priv->virq_dma);
5375d07b786SDaniel Hellstrom ack = 1;
5385d07b786SDaniel Hellstrom }
5395d07b786SDaniel Hellstrom
5405d07b786SDaniel Hellstrom /*
5415d07b786SDaniel Hellstrom * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
5425d07b786SDaniel Hellstrom * Controller, this must be done after IRQ sources have been handled to
5435d07b786SDaniel Hellstrom * avoid double IRQ generation
5445d07b786SDaniel Hellstrom */
5455d07b786SDaniel Hellstrom if (ack)
5465d07b786SDaniel Hellstrom desc->irq_data.chip->irq_eoi(&desc->irq_data);
5475d07b786SDaniel Hellstrom }
5485d07b786SDaniel Hellstrom
5495d07b786SDaniel Hellstrom /* Create a virtual IRQ */
grpci2_build_device_irq(unsigned int irq)5505d07b786SDaniel Hellstrom static unsigned int grpci2_build_device_irq(unsigned int irq)
5515d07b786SDaniel Hellstrom {
5525d07b786SDaniel Hellstrom unsigned int virq = 0, pil;
5535d07b786SDaniel Hellstrom
5545d07b786SDaniel Hellstrom pil = 1 << 8;
5555d07b786SDaniel Hellstrom virq = irq_alloc(irq, pil);
5565d07b786SDaniel Hellstrom if (virq == 0)
5575d07b786SDaniel Hellstrom goto out;
5585d07b786SDaniel Hellstrom
5595d07b786SDaniel Hellstrom irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
5605d07b786SDaniel Hellstrom "pcilvl");
5615d07b786SDaniel Hellstrom irq_set_chip_data(virq, (void *)irq);
5625d07b786SDaniel Hellstrom
5635d07b786SDaniel Hellstrom out:
5645d07b786SDaniel Hellstrom return virq;
5655d07b786SDaniel Hellstrom }
5665d07b786SDaniel Hellstrom
grpci2_hw_init(struct grpci2_priv * priv)5673731e199SSam Ravnborg static void grpci2_hw_init(struct grpci2_priv *priv)
5685d07b786SDaniel Hellstrom {
5695d07b786SDaniel Hellstrom u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
5703731e199SSam Ravnborg struct grpci2_regs __iomem *regs = priv->regs;
5715d07b786SDaniel Hellstrom int i;
5725d07b786SDaniel Hellstrom struct grpci2_barcfg *barcfg = priv->tgtbars;
5735d07b786SDaniel Hellstrom
5745d07b786SDaniel Hellstrom /* Reset any earlier setup */
5755d07b786SDaniel Hellstrom if (priv->do_reset) {
5765d07b786SDaniel Hellstrom printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
5775d07b786SDaniel Hellstrom REGSTORE(regs->ctrl, CTRL_RESET);
5785d07b786SDaniel Hellstrom ssleep(1); /* Wait for boards to settle */
5795d07b786SDaniel Hellstrom }
5805d07b786SDaniel Hellstrom REGSTORE(regs->ctrl, 0);
5815d07b786SDaniel Hellstrom REGSTORE(regs->sts_cap, ~0); /* Clear Status */
5825d07b786SDaniel Hellstrom REGSTORE(regs->dma_ctrl, 0);
5835d07b786SDaniel Hellstrom REGSTORE(regs->dma_bdbase, 0);
5845d07b786SDaniel Hellstrom
5855d07b786SDaniel Hellstrom /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
5865d07b786SDaniel Hellstrom REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
5875d07b786SDaniel Hellstrom
5885d07b786SDaniel Hellstrom /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
5895d07b786SDaniel Hellstrom * Each AHB master has it's own mapping registers. Max 16 AHB masters.
5905d07b786SDaniel Hellstrom */
5915d07b786SDaniel Hellstrom for (i = 0; i < 16; i++)
5925d07b786SDaniel Hellstrom REGSTORE(regs->ahbmst_map[i], priv->pci_area);
5935d07b786SDaniel Hellstrom
5945d07b786SDaniel Hellstrom /* Get the GRPCI2 Host PCI ID */
595a2956428SDaniel Hellstrom grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
5965d07b786SDaniel Hellstrom
5975d07b786SDaniel Hellstrom /* Get address to first (always defined) capability structure */
598a2956428SDaniel Hellstrom grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
5995d07b786SDaniel Hellstrom
6005d07b786SDaniel Hellstrom /* Enable/Disable Byte twisting */
601a2956428SDaniel Hellstrom grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
6025d07b786SDaniel Hellstrom io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
603a2956428SDaniel Hellstrom grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
6045d07b786SDaniel Hellstrom
6055d07b786SDaniel Hellstrom /* Setup the Host's PCI Target BARs for other peripherals to access,
6065d07b786SDaniel Hellstrom * and do DMA to the host's memory. The target BARs can be sized and
6075d07b786SDaniel Hellstrom * enabled individually.
6085d07b786SDaniel Hellstrom *
6095d07b786SDaniel Hellstrom * User may set custom target BARs, but default is:
6105d07b786SDaniel Hellstrom * The first BARs is used to map kernel low (DMA is part of normal
6115d07b786SDaniel Hellstrom * region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
6125d07b786SDaniel Hellstrom * PCI bus, the other BARs are disabled. We assume that the first BAR
6135d07b786SDaniel Hellstrom * is always available.
6145d07b786SDaniel Hellstrom */
6155d07b786SDaniel Hellstrom for (i = 0; i < 6; i++) {
6165d07b786SDaniel Hellstrom if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
6175d07b786SDaniel Hellstrom /* Target BARs must have the proper alignment */
6185d07b786SDaniel Hellstrom ahbadr = barcfg[i].ahbadr;
6195d07b786SDaniel Hellstrom pciadr = barcfg[i].pciadr;
6205d07b786SDaniel Hellstrom bar_sz = ((pciadr - 1) & ~pciadr) + 1;
6215d07b786SDaniel Hellstrom } else {
6225d07b786SDaniel Hellstrom if (i == 0) {
6235d07b786SDaniel Hellstrom /* Map main memory */
6245d07b786SDaniel Hellstrom bar_sz = 0xf0000008; /* 256MB prefetchable */
6255d07b786SDaniel Hellstrom ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
6265d07b786SDaniel Hellstrom (unsigned long) &_end));
6275d07b786SDaniel Hellstrom pciadr = ahbadr;
6285d07b786SDaniel Hellstrom } else {
6295d07b786SDaniel Hellstrom bar_sz = 0;
6305d07b786SDaniel Hellstrom ahbadr = 0;
6315d07b786SDaniel Hellstrom pciadr = 0;
6325d07b786SDaniel Hellstrom }
6335d07b786SDaniel Hellstrom }
634a2956428SDaniel Hellstrom grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
635a2956428SDaniel Hellstrom bar_sz);
636a2956428SDaniel Hellstrom grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
637a2956428SDaniel Hellstrom grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
6385d07b786SDaniel Hellstrom printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
6395d07b786SDaniel Hellstrom i, pciadr, ahbadr);
6405d07b786SDaniel Hellstrom }
6415d07b786SDaniel Hellstrom
6425d07b786SDaniel Hellstrom /* set as bus master and enable pci memory responses */
643a2956428SDaniel Hellstrom grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
6445d07b786SDaniel Hellstrom data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
645a2956428SDaniel Hellstrom grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
6465d07b786SDaniel Hellstrom
6475d07b786SDaniel Hellstrom /* Enable Error respone (CPU-TRAP) on illegal memory access. */
6485d07b786SDaniel Hellstrom REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
6495d07b786SDaniel Hellstrom }
6505d07b786SDaniel Hellstrom
grpci2_jump_interrupt(int irq,void * arg)6515d07b786SDaniel Hellstrom static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
6525d07b786SDaniel Hellstrom {
6535d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
6545d07b786SDaniel Hellstrom return IRQ_NONE;
6555d07b786SDaniel Hellstrom }
6565d07b786SDaniel Hellstrom
6575d07b786SDaniel Hellstrom /* Handle GRPCI2 Error Interrupt */
grpci2_err_interrupt(int irq,void * arg)6585d07b786SDaniel Hellstrom static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
6595d07b786SDaniel Hellstrom {
6605d07b786SDaniel Hellstrom struct grpci2_priv *priv = arg;
6613731e199SSam Ravnborg struct grpci2_regs __iomem *regs = priv->regs;
6625d07b786SDaniel Hellstrom unsigned int status;
6635d07b786SDaniel Hellstrom
6645d07b786SDaniel Hellstrom status = REGLOAD(regs->sts_cap);
6655d07b786SDaniel Hellstrom if ((status & STS_ERR_IRQ) == 0)
6665d07b786SDaniel Hellstrom return IRQ_NONE;
6675d07b786SDaniel Hellstrom
6685d07b786SDaniel Hellstrom if (status & STS_IPARERR)
6695d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: Parity Error\n");
6705d07b786SDaniel Hellstrom
6715d07b786SDaniel Hellstrom if (status & STS_ITGTABRT)
6725d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: Target Abort\n");
6735d07b786SDaniel Hellstrom
6745d07b786SDaniel Hellstrom if (status & STS_IMSTABRT)
6755d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: Master Abort\n");
6765d07b786SDaniel Hellstrom
6775d07b786SDaniel Hellstrom if (status & STS_ISYSERR)
6785d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: System Error\n");
6795d07b786SDaniel Hellstrom
6805d07b786SDaniel Hellstrom /* Clear handled INT TYPE IRQs */
6815d07b786SDaniel Hellstrom REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
6825d07b786SDaniel Hellstrom
6835d07b786SDaniel Hellstrom return IRQ_HANDLED;
6845d07b786SDaniel Hellstrom }
6855d07b786SDaniel Hellstrom
grpci2_of_probe(struct platform_device * ofdev)6867c9503b8SGreg Kroah-Hartman static int grpci2_of_probe(struct platform_device *ofdev)
6875d07b786SDaniel Hellstrom {
6883731e199SSam Ravnborg struct grpci2_regs __iomem *regs;
6895d07b786SDaniel Hellstrom struct grpci2_priv *priv;
6905d07b786SDaniel Hellstrom int err, i, len;
6915d07b786SDaniel Hellstrom const int *tmp;
6925d07b786SDaniel Hellstrom unsigned int capability;
6935d07b786SDaniel Hellstrom
6945d07b786SDaniel Hellstrom if (grpci2priv) {
6955d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
6965d07b786SDaniel Hellstrom return -ENODEV;
6975d07b786SDaniel Hellstrom }
6985d07b786SDaniel Hellstrom
6995d07b786SDaniel Hellstrom if (ofdev->num_resources < 3) {
7005d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
7015d07b786SDaniel Hellstrom return -EIO;
7025d07b786SDaniel Hellstrom }
7035d07b786SDaniel Hellstrom
7045d07b786SDaniel Hellstrom /* Find Device Address */
7055d07b786SDaniel Hellstrom regs = of_ioremap(&ofdev->resource[0], 0,
7065d07b786SDaniel Hellstrom resource_size(&ofdev->resource[0]),
7075d07b786SDaniel Hellstrom "grlib-grpci2 regs");
7085d07b786SDaniel Hellstrom if (regs == NULL) {
7095d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: ioremap failed\n");
7105d07b786SDaniel Hellstrom return -EIO;
7115d07b786SDaniel Hellstrom }
7125d07b786SDaniel Hellstrom
7135d07b786SDaniel Hellstrom /*
7145d07b786SDaniel Hellstrom * Check that we're in Host Slot and that we can act as a Host Bridge
7155d07b786SDaniel Hellstrom * and not only as target.
7165d07b786SDaniel Hellstrom */
7175d07b786SDaniel Hellstrom capability = REGLOAD(regs->sts_cap);
7185d07b786SDaniel Hellstrom if ((capability & STS_HOST) || !(capability & STS_MST)) {
7195d07b786SDaniel Hellstrom printk(KERN_INFO "GRPCI2: not in host system slot\n");
7205d07b786SDaniel Hellstrom err = -EIO;
7215d07b786SDaniel Hellstrom goto err1;
7225d07b786SDaniel Hellstrom }
7235d07b786SDaniel Hellstrom
7245d07b786SDaniel Hellstrom priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
7255d07b786SDaniel Hellstrom if (grpci2priv == NULL) {
7265d07b786SDaniel Hellstrom err = -ENOMEM;
7275d07b786SDaniel Hellstrom goto err1;
7285d07b786SDaniel Hellstrom }
7295d07b786SDaniel Hellstrom priv->regs = regs;
7305d07b786SDaniel Hellstrom priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
7315d07b786SDaniel Hellstrom priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
7325d07b786SDaniel Hellstrom
7335d07b786SDaniel Hellstrom printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
7345d07b786SDaniel Hellstrom
7355d07b786SDaniel Hellstrom /* Byte twisting should be made configurable from kernel command line */
7365d07b786SDaniel Hellstrom priv->bt_enabled = 1;
7375d07b786SDaniel Hellstrom
7385d07b786SDaniel Hellstrom /* Let user do custom Target BAR assignment */
7395d07b786SDaniel Hellstrom tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
7405d07b786SDaniel Hellstrom if (tmp && (len == 2*4*6))
7415d07b786SDaniel Hellstrom memcpy(priv->tgtbars, tmp, 2*4*6);
7425d07b786SDaniel Hellstrom else
7435d07b786SDaniel Hellstrom memset(priv->tgtbars, -1, 2*4*6);
7445d07b786SDaniel Hellstrom
7455d07b786SDaniel Hellstrom /* Limit IRQ unmasking in irq_mode 2 and 3 */
7465d07b786SDaniel Hellstrom tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
7475d07b786SDaniel Hellstrom if (tmp && (len == 4))
7485d07b786SDaniel Hellstrom priv->do_reset = *tmp;
7495d07b786SDaniel Hellstrom else
7505d07b786SDaniel Hellstrom priv->irq_mask = 0xf;
7515d07b786SDaniel Hellstrom
7525d07b786SDaniel Hellstrom /* Optional PCI reset. Force PCI reset on startup */
7535d07b786SDaniel Hellstrom tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
7545d07b786SDaniel Hellstrom if (tmp && (len == 4))
7555d07b786SDaniel Hellstrom priv->do_reset = *tmp;
7565d07b786SDaniel Hellstrom else
7575d07b786SDaniel Hellstrom priv->do_reset = 0;
7585d07b786SDaniel Hellstrom
7595d07b786SDaniel Hellstrom /* Find PCI Memory, I/O and Configuration Space Windows */
7605d07b786SDaniel Hellstrom priv->pci_area = ofdev->resource[1].start;
7615d07b786SDaniel Hellstrom priv->pci_area_end = ofdev->resource[1].end+1;
7625d07b786SDaniel Hellstrom priv->pci_io = ofdev->resource[2].start;
7635d07b786SDaniel Hellstrom priv->pci_conf = ofdev->resource[2].start + 0x10000;
7645d07b786SDaniel Hellstrom priv->pci_conf_end = priv->pci_conf + 0x10000;
7655d07b786SDaniel Hellstrom priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
7665d07b786SDaniel Hellstrom if (!priv->pci_io_va) {
7675d07b786SDaniel Hellstrom err = -EIO;
7685d07b786SDaniel Hellstrom goto err2;
7695d07b786SDaniel Hellstrom }
7705d07b786SDaniel Hellstrom
7715d07b786SDaniel Hellstrom printk(KERN_INFO
7725d07b786SDaniel Hellstrom "GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
7735d07b786SDaniel Hellstrom " I/O SPACE [0x%08lx - 0x%08lx]\n"
7745d07b786SDaniel Hellstrom " CONFIG SPACE [0x%08lx - 0x%08lx]\n",
7755d07b786SDaniel Hellstrom priv->pci_area, priv->pci_area_end-1,
7765d07b786SDaniel Hellstrom priv->pci_io, priv->pci_conf-1,
7775d07b786SDaniel Hellstrom priv->pci_conf, priv->pci_conf_end-1);
7785d07b786SDaniel Hellstrom
7795d07b786SDaniel Hellstrom /*
7805d07b786SDaniel Hellstrom * I/O Space resources in I/O Window mapped into Virtual Adr Space
7815d07b786SDaniel Hellstrom * We never use low 4KB because some devices seem have problems using
7825d07b786SDaniel Hellstrom * address 0.
7835d07b786SDaniel Hellstrom */
7845d07b786SDaniel Hellstrom memset(&priv->info.io_space, 0, sizeof(struct resource));
7855d07b786SDaniel Hellstrom priv->info.io_space.name = "GRPCI2 PCI I/O Space";
7865d07b786SDaniel Hellstrom priv->info.io_space.start = priv->pci_io_va + 0x1000;
7875d07b786SDaniel Hellstrom priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
7885d07b786SDaniel Hellstrom priv->info.io_space.flags = IORESOURCE_IO;
7895d07b786SDaniel Hellstrom
7905d07b786SDaniel Hellstrom /*
7915d07b786SDaniel Hellstrom * GRPCI2 has no prefetchable memory, map everything as
7925d07b786SDaniel Hellstrom * non-prefetchable memory
7935d07b786SDaniel Hellstrom */
7945d07b786SDaniel Hellstrom memset(&priv->info.mem_space, 0, sizeof(struct resource));
7955d07b786SDaniel Hellstrom priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
7965d07b786SDaniel Hellstrom priv->info.mem_space.start = priv->pci_area;
7975d07b786SDaniel Hellstrom priv->info.mem_space.end = priv->pci_area_end - 1;
7985d07b786SDaniel Hellstrom priv->info.mem_space.flags = IORESOURCE_MEM;
7995d07b786SDaniel Hellstrom
8005d07b786SDaniel Hellstrom if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
8015d07b786SDaniel Hellstrom goto err3;
8025d07b786SDaniel Hellstrom if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
8035d07b786SDaniel Hellstrom goto err4;
8045d07b786SDaniel Hellstrom
805aa90b694SDaniel Hellstrom /* setup maximum supported PCI buses */
806aa90b694SDaniel Hellstrom priv->info.busn.name = "GRPCI2 busn";
807aa90b694SDaniel Hellstrom priv->info.busn.start = 0;
808aa90b694SDaniel Hellstrom priv->info.busn.end = 255;
809aa90b694SDaniel Hellstrom
8105d07b786SDaniel Hellstrom grpci2_hw_init(priv);
8115d07b786SDaniel Hellstrom
8125d07b786SDaniel Hellstrom /*
8135d07b786SDaniel Hellstrom * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
8145d07b786SDaniel Hellstrom * Error IRQ always on PCI INTA.
8155d07b786SDaniel Hellstrom */
8165d07b786SDaniel Hellstrom if (priv->irq_mode < 2) {
8175d07b786SDaniel Hellstrom /* All PCI interrupts are shared using the same system IRQ */
8185d07b786SDaniel Hellstrom leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
8195d07b786SDaniel Hellstrom "pcilvl", 0);
8205d07b786SDaniel Hellstrom
8215d07b786SDaniel Hellstrom priv->irq_map[0] = grpci2_build_device_irq(1);
8225d07b786SDaniel Hellstrom priv->irq_map[1] = grpci2_build_device_irq(2);
8235d07b786SDaniel Hellstrom priv->irq_map[2] = grpci2_build_device_irq(3);
8245d07b786SDaniel Hellstrom priv->irq_map[3] = grpci2_build_device_irq(4);
8255d07b786SDaniel Hellstrom
8265d07b786SDaniel Hellstrom priv->virq_err = grpci2_build_device_irq(5);
8275d07b786SDaniel Hellstrom if (priv->irq_mode & 1)
8285d07b786SDaniel Hellstrom priv->virq_dma = ofdev->archdata.irqs[1];
8295d07b786SDaniel Hellstrom else
8305d07b786SDaniel Hellstrom priv->virq_dma = grpci2_build_device_irq(6);
8315d07b786SDaniel Hellstrom
8325d07b786SDaniel Hellstrom /* Enable IRQs on LEON IRQ controller */
8335d07b786SDaniel Hellstrom err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
8345d07b786SDaniel Hellstrom "GRPCI2_JUMP", priv);
8355d07b786SDaniel Hellstrom if (err)
8365d07b786SDaniel Hellstrom printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
8375d07b786SDaniel Hellstrom } else {
8385d07b786SDaniel Hellstrom /* All PCI interrupts have an unique IRQ interrupt */
8395d07b786SDaniel Hellstrom for (i = 0; i < 4; i++) {
8405d07b786SDaniel Hellstrom /* Make LEON IRQ layer handle level IRQ by acking */
8415d07b786SDaniel Hellstrom leon_update_virq_handling(ofdev->archdata.irqs[i],
8425d07b786SDaniel Hellstrom handle_fasteoi_irq, "pcilvl",
8435d07b786SDaniel Hellstrom 1);
8445d07b786SDaniel Hellstrom priv->irq_map[i] = ofdev->archdata.irqs[i];
8455d07b786SDaniel Hellstrom }
8465d07b786SDaniel Hellstrom priv->virq_err = priv->irq_map[0];
8475d07b786SDaniel Hellstrom if (priv->irq_mode & 1)
8485d07b786SDaniel Hellstrom priv->virq_dma = ofdev->archdata.irqs[4];
8495d07b786SDaniel Hellstrom else
8505d07b786SDaniel Hellstrom priv->virq_dma = priv->irq_map[0];
8515d07b786SDaniel Hellstrom
8525d07b786SDaniel Hellstrom /* Unmask all PCI interrupts, request_irq will not do that */
8535d07b786SDaniel Hellstrom REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
8545d07b786SDaniel Hellstrom }
8555d07b786SDaniel Hellstrom
8565d07b786SDaniel Hellstrom /* Setup IRQ handler for non-configuration space access errors */
8575d07b786SDaniel Hellstrom err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
8585d07b786SDaniel Hellstrom "GRPCI2_ERR", priv);
8595d07b786SDaniel Hellstrom if (err) {
8605d07b786SDaniel Hellstrom printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
8615d07b786SDaniel Hellstrom goto err5;
8625d07b786SDaniel Hellstrom }
8635d07b786SDaniel Hellstrom
8645d07b786SDaniel Hellstrom /*
8655d07b786SDaniel Hellstrom * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
8665d07b786SDaniel Hellstrom * is called by the PCI Device drivers
8675d07b786SDaniel Hellstrom */
8685d07b786SDaniel Hellstrom REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
8695d07b786SDaniel Hellstrom
8705d07b786SDaniel Hellstrom /* Init common layer and scan buses */
8715d07b786SDaniel Hellstrom priv->info.ops = &grpci2_ops;
8725d07b786SDaniel Hellstrom priv->info.map_irq = grpci2_map_irq;
8735d07b786SDaniel Hellstrom leon_pci_init(ofdev, &priv->info);
8745d07b786SDaniel Hellstrom
8755d07b786SDaniel Hellstrom return 0;
8765d07b786SDaniel Hellstrom
8775d07b786SDaniel Hellstrom err5:
8785d07b786SDaniel Hellstrom release_resource(&priv->info.io_space);
8795d07b786SDaniel Hellstrom err4:
8805d07b786SDaniel Hellstrom release_resource(&priv->info.mem_space);
8815d07b786SDaniel Hellstrom err3:
8825d07b786SDaniel Hellstrom err = -ENOMEM;
8833731e199SSam Ravnborg iounmap((void __iomem *)priv->pci_io_va);
8845d07b786SDaniel Hellstrom err2:
8855d07b786SDaniel Hellstrom kfree(priv);
8865d07b786SDaniel Hellstrom err1:
8875d07b786SDaniel Hellstrom of_iounmap(&ofdev->resource[0], regs,
8885d07b786SDaniel Hellstrom resource_size(&ofdev->resource[0]));
8895d07b786SDaniel Hellstrom return err;
8905d07b786SDaniel Hellstrom }
8915d07b786SDaniel Hellstrom
892*73f06dadSSam Ravnborg static const struct of_device_id grpci2_of_match[] = {
8935d07b786SDaniel Hellstrom {
8945d07b786SDaniel Hellstrom .name = "GAISLER_GRPCI2",
8955d07b786SDaniel Hellstrom },
8965d07b786SDaniel Hellstrom {
8975d07b786SDaniel Hellstrom .name = "01_07c",
8985d07b786SDaniel Hellstrom },
8995d07b786SDaniel Hellstrom {},
9005d07b786SDaniel Hellstrom };
9015d07b786SDaniel Hellstrom
9025d07b786SDaniel Hellstrom static struct platform_driver grpci2_of_driver = {
9035d07b786SDaniel Hellstrom .driver = {
9045d07b786SDaniel Hellstrom .name = "grpci2",
9055d07b786SDaniel Hellstrom .of_match_table = grpci2_of_match,
9065d07b786SDaniel Hellstrom },
9075d07b786SDaniel Hellstrom .probe = grpci2_of_probe,
9085d07b786SDaniel Hellstrom };
9095d07b786SDaniel Hellstrom
grpci2_init(void)9105d07b786SDaniel Hellstrom static int __init grpci2_init(void)
9115d07b786SDaniel Hellstrom {
9125d07b786SDaniel Hellstrom return platform_driver_register(&grpci2_of_driver);
9135d07b786SDaniel Hellstrom }
9145d07b786SDaniel Hellstrom
9155d07b786SDaniel Hellstrom subsys_initcall(grpci2_init);
916