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/openbmc/linux/drivers/phy/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for TI platforms
6 tristate "TI DA8xx USB PHY Driver"
11 Enable this to support the USB PHY on DA8xx SoCs.
13 This driver controls both the USB 1.1 PHY and the USB 2.0 PHY.
16 tristate "TI dm816x USB PHY driver"
33 This option enables support for TI AM654 SerDes PHY used for
37 tristate "TI J721E WIZ (SERDES Wrapper) support"
47 SoC. WIZ is a serdes wrapper used to configure some of the input
53 tristate "OMAP CONTROL PHY Driver"
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/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dk3-am654-ddrss.txt5 Synopys DDR controller, Synopsis DDR phy and wrapper logic to
9 configuring the DDRSS registers and using the buitin PHY
15 --------------------
16 - compatible: Shall be: "ti,am654-ddrss"
17 - reg-names ss - Map the sub system wrapper logic region
18 ctl - Map the controller region
19 phy - Map the PHY region
20 - reg: Contains the register map per reg-names.
21 - power-domains: Should contain a phandle to a PM domain provider node
24 doc/device-tree-bindings/power/ti,sci-pm-domain.txt
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/openbmc/linux/arch/powerpc/boot/dts/
H A Dacadia.dts11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <0>; /* Filled in by wrapper */
35 timebase-frequency = <0>; /* Filled in by wrapper */
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sa8775p-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
16 See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h
20 const: qcom,sa8775p-gcc
24 - description: XO reference clock
25 - description: Sleep clock
26 - description: UFS memory first RX symbol clock
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H A Dqcom,sm8550-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
20 const: qcom,sm8550-gcc
24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source
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H A Dqcom,gcc-sm8450.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
20 const: qcom,gcc-sm8450
24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source (Optional clock)
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H A Dqcom,gcc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
20 const: qcom,gcc-sm8350
24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source (Optional clock)
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H A Dqcom,gcc-sc7280.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
16 See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
20 const: qcom,gcc-sc7280
24 - description: Board XO source
25 - description: Board active XO source
26 - description: Sleep clock source
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H A Dqcom,ipq5332-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
19 - $ref: qcom,gcc.yaml#
23 const: qcom,ipq5332-gcc
27 - description: Board XO clock source
28 - description: Sleep clock source
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H A Dqcom,qdu1000-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Imran Shaik <quic_imrashai@quicinc.com>
17 See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h
21 const: qcom,qdu1000-gcc
25 - description: Board XO source
26 - description: Sleep clock source
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/openbmc/u-boot/drivers/net/phy/
H A Dmv88e61xx.c1 // SPDX-License-Identifier: GPL-2.0+
14 * PHY driver for mv88e61xx ethernet switches.
16 * This driver configures the mv88e61xx for basic use as a PHY. The switch
19 * traffic from each PHY port only to the CPU port, and from the CPU port to
20 * any PHY port.
22 * The configuration determines which PHY ports to activate using the
25 * connected to unless it is connected over a PHY interface (not MII).
43 #define PORT_MASK ((1 << PORT_COUNT) - 1)
73 /* Phy registers */
81 /* Phy page numbers */
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/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dsata.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * SATA Wrapper Register map
12 /* SATA Wrapper module */
14 /* SATA PHY Module */
17 /* SATA Wrapper register offsets */
/openbmc/linux/drivers/pci/controller/
H A Dpcie-iproc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2014-2015 Broadcom Corporation
10 * enum iproc_pcie_type - iProc PCIe interface type
11 * @IPROC_PCIE_PAXB_BCMA: BCMA-based host controllers
12 * @IPROC_PCIE_PAXB: PAXB-based host controllers for
14 * @IPROC_PCIE_PAXB_V2: PAXB-based host controllers for Stingray SoCs
15 * @IPROC_PCIE_PAXC: PAXC-based host controllers
16 * @IPROC_PCIE_PAXC_V2: PAXC-based host controllers (second generation)
18 * PAXB is the wrapper used in root complex that can be connected to an
21 * PAXC is the wrapper used in root complex dedicated for internal emulated
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/openbmc/u-boot/drivers/usb/ulpi/
H A DKconfig7 Select ULPI viewport (SoC-side interface to ULPI) implementation
9 UTMI (USB PHY) via ULPI interface.
28 Select to commnicate with USB PHY via ULPI interface.
29 ULPI is wrapper on UTMI+ core that is used as
30 PHY Transreceiver for USB controllers.
/openbmc/u-boot/drivers/usb/musb/
H A Dam35x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * am35x.h - TI's AM35x platform specific usb wrapper definitions.
18 /* Base address of musb wrapper */
28 * AM35x platform USB wrapper register overlay.
64 /* USB 2.0 PHY Control */
H A Dam35x.c1 // SPDX-License-Identifier: GPL-2.0+
3 * am35x.c - TI's AM35x platform specific usb wrapper functions.
24 * Enable the USB phy
31 devconf2 = readl(&am35x_scm_general_regs->devconf2); in phy_on()
39 writel(devconf2, &am35x_scm_general_regs->devconf2); in phy_on()
41 /* wait until the USB phy is turned on */ in phy_on()
43 while (timeout--) in phy_on()
44 if (readl(&am35x_scm_general_regs->devconf2) & DEVCONF2_PHYCKGD) in phy_on()
47 /* USB phy was not turned on */ in phy_on()
52 * Disable the USB phy
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/openbmc/linux/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
29 /* DSI wrapper registers & bit definitions */
31 #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
35 #define DSI_WCR 0x0404 /* Wrapper Control Reg */
38 #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
42 #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
46 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
89 writel(val, dsi->base + reg); in dsi_write()
94 return readl(dsi->base + reg); in dsi_read()
150 return -EINVAL; in dsi_pll_get_params()
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/openbmc/u-boot/drivers/net/
H A Dsmc911x.c1 // SPDX-License-Identifier: GPL-2.0+
24 uchar *m = dev->enetaddr; in smc911x_handle_mac_address()
35 u8 phy, u8 reg, u16 *val) in smc911x_eth_phy_read() argument
40 smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | in smc911x_eth_phy_read()
52 u8 phy, u8 reg, u16 val) in smc911x_eth_phy_write() argument
59 phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); in smc911x_eth_phy_write()
96 if ((timeout--) == 0) in smc911x_phy_configure()
103 printf(DRIVERNAME ": phy initialized\n"); in smc911x_phy_configure()
130 struct chip_id *id = dev->priv; in smc911x_init()
132 printf(DRIVERNAME ": detected %s controller\n", id->name); in smc911x_init()
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/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dda8xx-usb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
17 /* Base address of da8xx usb0 wrapper */
27 * DA8xx platform USB wrapper register overlay.
64 /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
/openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
16 #include <sound/omap-hdmi-audio.h>
20 /* HDMI Wrapper */
68 /* HDMI PHY */
276 /* HDMI wrapper funcs */
305 /* HDMI PHY funcs */
306 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
308 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
309 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
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/openbmc/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
15 #include <sound/omap-hdmi-audio.h>
24 /* HDMI Wrapper */
72 /* HDMI PHY */
295 /* HDMI wrapper funcs */
323 /* HDMI PHY funcs */
324 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
326 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
327 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy,
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,msm8996-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (MSM8996 PCIe)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
18 const: qcom,msm8996-qmp-pcie-phy
22 - description: serdes
24 "#address-cells":
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H A Dqcom,msm8996-qmp-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB, MSM8996)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
17 qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
22 - qcom,ipq6018-qmp-usb3-phy
23 - qcom,ipq8074-qmp-usb3-phy
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dti,am62-usb.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI's AM62 wrapper module for the Synopsys USBSS-DRD controller
10 - Aswath Govindraju <a-govindraju@ti.com>
14 const: ti,am62-usb
21 power-domains:
25 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
32 clock-names:
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/openbmc/linux/drivers/usb/core/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * A wrapper for multiple PHYs which passes all phy_* function calls to
4 * multiple (actual) PHY devices. This is comes handy when initializing
12 #include <linux/phy/phy.h>
15 #include "phy.h"
18 struct phy *phy; member
26 struct phy *phy; in usb_phy_roothub_add_phy() local
28 phy = devm_of_phy_get_by_index(dev, dev->of_node, index); in usb_phy_roothub_add_phy()
29 if (IS_ERR(phy)) { in usb_phy_roothub_add_phy()
30 if (PTR_ERR(phy) == -ENODEV) in usb_phy_roothub_add_phy()
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