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/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dk3-am654-ddrss.txt5 Synopys DDR controller, Synopsis DDR phy and wrapper logic to
9 configuring the DDRSS registers and using the buitin PHY
15 --------------------
16 - compatible: Shall be: "ti,am654-ddrss"
17 - reg-names ss - Map the sub system wrapper logic region
18 ctl - Map the controller region
19 phy - Map the PHY region
20 - reg: Contains the register map per reg-names.
21 - power-domains: Should contain a phandle to a PM domain provider node
24 doc/device-tree-bindings/power/ti,sci-pm-domain.txt
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/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dsata.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * SATA Wrapper Register map
12 /* SATA Wrapper module */
14 /* SATA PHY Module */
17 /* SATA Wrapper register offsets */
/openbmc/u-boot/drivers/usb/ulpi/
H A DKconfig7 Select ULPI viewport (SoC-side interface to ULPI) implementation
9 UTMI (USB PHY) via ULPI interface.
28 Select to commnicate with USB PHY via ULPI interface.
29 ULPI is wrapper on UTMI+ core that is used as
30 PHY Transreceiver for USB controllers.
/openbmc/u-boot/drivers/net/phy/
H A Dmv88e61xx.c1 // SPDX-License-Identifier: GPL-2.0+
14 * PHY driver for mv88e61xx ethernet switches.
16 * This driver configures the mv88e61xx for basic use as a PHY. The switch
19 * traffic from each PHY port only to the CPU port, and from the CPU port to
20 * any PHY port.
22 * The configuration determines which PHY ports to activate using the
25 * connected to unless it is connected over a PHY interface (not MII).
43 #define PORT_MASK ((1 << PORT_COUNT) - 1)
73 /* Phy registers */
81 /* Phy page numbers */
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/openbmc/u-boot/drivers/usb/musb/
H A Dam35x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * am35x.h - TI's AM35x platform specific usb wrapper definitions.
18 /* Base address of musb wrapper */
28 * AM35x platform USB wrapper register overlay.
64 /* USB 2.0 PHY Control */
H A Dam35x.c1 // SPDX-License-Identifier: GPL-2.0+
3 * am35x.c - TI's AM35x platform specific usb wrapper functions.
24 * Enable the USB phy
31 devconf2 = readl(&am35x_scm_general_regs->devconf2); in phy_on()
39 writel(devconf2, &am35x_scm_general_regs->devconf2); in phy_on()
41 /* wait until the USB phy is turned on */ in phy_on()
43 while (timeout--) in phy_on()
44 if (readl(&am35x_scm_general_regs->devconf2) & DEVCONF2_PHYCKGD) in phy_on()
47 /* USB phy was not turned on */ in phy_on()
52 * Disable the USB phy
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/openbmc/u-boot/drivers/net/
H A Dsmc911x.c1 // SPDX-License-Identifier: GPL-2.0+
24 uchar *m = dev->enetaddr; in smc911x_handle_mac_address()
35 u8 phy, u8 reg, u16 *val) in smc911x_eth_phy_read() argument
40 smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | in smc911x_eth_phy_read()
52 u8 phy, u8 reg, u16 val) in smc911x_eth_phy_write() argument
59 phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); in smc911x_eth_phy_write()
96 if ((timeout--) == 0) in smc911x_phy_configure()
103 printf(DRIVERNAME ": phy initialized\n"); in smc911x_phy_configure()
130 struct chip_id *id = dev->priv; in smc911x_init()
132 printf(DRIVERNAME ": detected %s controller\n", id->name); in smc911x_init()
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H A De1000.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
10 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
36 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
49 /* I/O wrapper functions */
51 writel((value), ((a)->hw_addr + E1000_##reg))
53 readl((a)->hw_addr + E1000_##reg)
55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
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/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dda8xx-usb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
17 /* Base address of da8xx usb0 wrapper */
27 * DA8xx platform USB wrapper register overlay.
64 /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
/openbmc/u-boot/drivers/net/ti/
H A Ddavinci_emac.c1 // SPDX-License-Identifier: GPL-2.0+
10 * ----------------------------------------------------------------------------
14 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
18 * ----------------------------------------------------------------------------
21 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
22 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
44 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; in BD_TO_HW()
52 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; in HW_TO_BD()
67 EMAC_MDIO_CLOCK_FREQ) - 1)
102 /* PHY address for a discovered PHY (0xff - not found) */
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H A Ddavinci_emac.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Based on: mach-davinci/emac_defs.h
42 /* PHY Configuration register */
230 /* EMAC Wrapper Registers Structure */
/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
14 #include <power-domain.h>
18 #include "k3-am654-ddrss.h"
22 /* DDRSS PHY configuration register fixed values */
26 * struct am654_ddrss_desc - Description of ddrss integration.
28 * @ddrss_ss_cfg: DDRSS wrapper logic region base address
30 * @ddrss_phy_cfg: DDRSS PHY region base address
60 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
61 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
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H A Dk3-am654-ddrss.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
13 /* DDRSS subsystem wrapper logic registers */
179 /* DDRSS PHY configuration registers */
/openbmc/u-boot/drivers/usb/musb-new/
H A Dmusb_dsps.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/dma-mapping.h>
34 #include "linux-compat.h"
56 * DSPS musb wrapper register offset.
57 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
137 const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
142 * dsps_musb_enable - enable interrupts
151 struct device *dev = musb->controller; in dsps_musb_enable()
152 struct platform_device *pdev = to_platform_device(dev->parent); in dsps_musb_enable()
154 const struct dsps_musb_wrapper *wrp = glue->wrp; in dsps_musb_enable()
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H A Dti-musb.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <dm/device-internal.h>
23 /* USB 2.0 PHY Control */
36 if (!platdata->ctrl_mod_base) in ti_musb_set_phy_power()
40 clrsetbits_le32(platdata->ctrl_mod_base, in ti_musb_set_phy_power()
44 clrsetbits_le32(platdata->ctrl_mod_base, 0, in ti_musb_set_phy_power()
53 const void *fdt = gd->fdt_blob; in ti_musb_get_usb_index()
66 return -ENOENT; in ti_musb_get_usb_index()
75 return -ENOENT; in ti_musb_get_usb_index()
81 const void *fdt = gd->fdt_blob; in ti_musb_ofdata_to_platdata()
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/openbmc/u-boot/drivers/tpm/
H A Dtpm_tis.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * struct tpm_tis_phy_ops - low-level TPM bus operations
28 /* read_bytes() - Read a number of bytes from the device
39 /* write_bytes() - Read a number of bytes from the device
50 /* read32() - Read a 32bit value of the device
59 /* write32() - write a 32bit value to the device
202 * tpm_tis_open - Open the device and request locality 0
210 * tpm_tis_close - Close the device and release locality
217 /** tpm_tis_cleanup - Get the device in ready state and release locality
225 * tpm_tis_send - send data to the device
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/openbmc/u-boot/include/fsl-mc/
H A Dfsl_dpmac.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Freescale Layerscape MC I/O wrapper
5 * Copyright 2015-2016 Freescale Semiconductor, Inc.
35 MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->mac_id)
44 MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\
45 MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
46 MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\
47 MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\
48 MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\
54 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
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/openbmc/u-boot/drivers/usb/dwc3/
H A Ddwc3-generic.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2018 Xilinx, Inc.
7 * Based on dwc3-omap.c.
11 #include <asm-generic/io.h>
13 #include <dm/device-internal.h>
15 #include <dwc3-uboot.h>
28 struct phy *phys;
36 struct dwc3 *dwc3 = &priv->dwc3; in dm_usb_gadget_handle_interrupts()
47 struct dwc3 *dwc3 = &priv->dwc3; in dwc3_generic_peripheral_probe()
49 rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys); in dwc3_generic_peripheral_probe()
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/openbmc/u-boot/include/linux/usb/
H A Dcomposite.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * composite.h -- framework for usb gadgets which are composite devices
5 * Copyright (C) 2006-2008 David Brownell
14 * functions within any single configuration, and (b) Multi-configuration
41 * struct usb_function - describes one function of a configuration
66 * @setup: Used for interface-specific control requests.
88 * a driver-specific instance structure to allows multiple activations. An
138 * ep_choose - select descriptor endpoint at current device speed
147 if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH) in ep_choose()
155 * struct usb_configuration - represents one gadget configuration
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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_engine.c1 // SPDX-License-Identifier: GPL-2.0
14 ((((e2) - (e1) + 1) > 33) && ((e1) < 67))
20 u8 byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM]; /* holds the bit status in the byte in wrapper func…
459 * MC PBS Reg Address at DDR PHY in ddr3_tip_ip_training()
469 * where n (0-3) represents M_CS number in ddr3_tip_ip_training()
473 * ADLL WR Reg Address at DDR PHY in ddr3_tip_ip_training()
478 /* ADLL RD Reg Address at DDR PHY */ in ddr3_tip_ip_training()
509 if (IS_BUS_ACTIVE(tm->bus_act_mask, pup_id) == 1) in ddr3_tip_ip_training()
549 /* wa for 16-bit mode: wait for all rfu tests to finish or timeout */ in ddr3_tip_ip_training()
582 …if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask)/* || tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS… in ddr3_tip_load_pattern_to_odpg()
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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0004-FF-A-v15-arm_ffa-introduce-Arm-FF-A-support.patch4 Subject: [PATCH] FF-A v15: arm_ffa: introduce Arm FF-A support
6 Add Arm FF-A support implementing Arm Firmware Framework for Armv8-A v1.0
8 The Firmware Framework for Arm A-profile processors (FF-A v1.0) [1]
13 This driver uses 64-bit registers as per SMCCCv1.2 spec and comes
14 on top of the SMCCC layer. The driver provides the FF-A ABIs needed for
15 querying the FF-A framework from the secure world.
18 32-bit data of the Xn registers.
20 All supported ABIs come with their 32-bit version except FFA_RXTX_MAP
21 which has 64-bit version supported.
23 Both 32-bit and 64-bit direct messaging are supported which allows both
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H A D0006-FF-A-v15-arm_ffa-introduce-sandbox-FF-A-support.patch4 Subject: [PATCH] FF-A v15: arm_ffa: introduce sandbox FF-A support
6 Emulate Secure World's FF-A ABIs and allow testing U-Boot FF-A support
8 Features of the sandbox FF-A support:
10 - Introduce an FF-A emulator
11 - Introduce an FF-A device driver for FF-A comms with emulated Secure World
12 - Provides test methods allowing to read the status of the inspected ABIs
14 The sandbox FF-A emulator supports only 64-bit direct messaging.
16 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
17 Reviewed-by: Simon Glass <sjg@chromium.org>
18 Upstream-Status: Submitted [cover letter: https://lore.kernel.org/all/20230713132847.176000-1-abdel…
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/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c2 * QEMU emulation of an RISC-V IOMMU
4 * Copyright (C) 2021-2023, Rivos Inc.
24 #include "hw/qdev-properties.h"
31 #include "riscv-iommu.h"
32 #include "riscv-iommu-bits.h"
33 #include "riscv-iommu-hpm.h"
41 #define PPN_DOWN(phy) ((phy) >> TARGET_PAGE_BITS) argument
58 RISCV_IOMMU_TRANS_TAG_VG, /* G-stage only */
66 uint64_t pscid:20; /* Process Soft-Context identifier */
68 uint64_t gscid:16; /* Guest Soft-Context identifier */
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/openbmc/qemu/hw/net/
H A Dvmxnet3.c14 * See the COPYING file in the top-level directory.
21 #include "hw/qdev-properties.h"
58 /* Link status: 1 - up, 0 - down. */
65 /* Number of interrupt vectors for non-MSIx modes */
136 ring->pa = pa; in DECLARE_CLASS_CHECKERS()
137 ring->size = size; in DECLARE_CLASS_CHECKERS()
138 ring->cell_size = cell_size; in DECLARE_CLASS_CHECKERS()
139 ring->gen = VMXNET3_INIT_GEN; in DECLARE_CLASS_CHECKERS()
140 ring->next = 0; in DECLARE_CLASS_CHECKERS()
150 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
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/openbmc/qemu/
H A DMAINTAINERS10 consult qemu-devel and not any specific individual privately.
23 W: Web-page with status/info
59 ------------------------------
63 L: qemu-devel@nongnu.org
72 R: Philippe Mathieu-Daudé <philmd@linaro.org>
75 F: docs/devel/build-environment.rst
76 F: docs/devel/code-of-conduct.rst
78 F: docs/devel/conflict-resolution.rst
80 F: docs/devel/submitting-a-patch.rst
81 F: docs/devel/submitting-a-pull-request.rst
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