Home
last modified time | relevance | path

Searched +full:phy +full:- +full:mode (Results 1 – 25 of 1038) sorted by relevance

12345678910>>...42

/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
[all …]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
[all …]
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
[all …]
/openbmc/linux/drivers/nfc/s3fwrn5/
H A Dphy_common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 struct phy_common *phy = phy_id; in s3fwrn5_phy_set_wake() local
21 mutex_lock(&phy->mutex); in s3fwrn5_phy_set_wake()
22 gpio_set_value(phy->gpio_fw_wake, wake); in s3fwrn5_phy_set_wake()
25 mutex_unlock(&phy->mutex); in s3fwrn5_phy_set_wake()
29 bool s3fwrn5_phy_power_ctrl(struct phy_common *phy, enum s3fwrn5_mode mode) in s3fwrn5_phy_power_ctrl() argument
31 if (phy->mode == mode) in s3fwrn5_phy_power_ctrl()
34 phy->mode = mode; in s3fwrn5_phy_power_ctrl()
36 gpio_set_value(phy->gpio_en, 1); in s3fwrn5_phy_power_ctrl()
37 gpio_set_value(phy->gpio_fw_wake, 0); in s3fwrn5_phy_power_ctrl()
[all …]
/openbmc/linux/drivers/phy/starfive/
H A Dphy-jh7110-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 PCIe 2.0 PHY driver
15 #include <linux/phy/phy.h>
37 struct phy *phy; member
44 enum phy_mode mode; member
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
56 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
[all …]
H A Dphy-jh7110-usb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 USB 2.0 PHY driver
14 #include <linux/phy/phy.h>
23 struct phy *phy; member
27 enum phy_mode mode; member
30 static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set) in usb2_set_ls_keepalive() argument
34 /* Host mode enable the LS speed keep-alive signal */ in usb2_set_ls_keepalive()
35 val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
41 writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
44 static int usb2_phy_set_mode(struct phy *_phy, in usb2_phy_set_mode()
[all …]
/openbmc/linux/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 HiSilicon Limited.
89 struct mipi_phy_params phy; member
122 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
155 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
156 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
157 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
191 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
/openbmc/linux/drivers/phy/hisilicon/
H A Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
17 #include <linux/phy/phy.h>
21 #include <dt-bindings/phy/phy.h>
49 struct phy *phy; member
50 struct histb_combphy_mode mode; member
56 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
74 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
76 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
81 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/openbmc/linux/include/linux/phy/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-lvds.h>
21 #include <linux/phy/phy-mipi-dphy.h>
23 struct phy;
55 * union phy_configure_opts - Opaque generic phy configuration
58 * the MIPI_DPHY phy mode.
62 * the LVDS phy mode.
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-pcb8290.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
9 /dts-v1/;
11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
15 compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
17 gpio-restart {
18 compatible = "gpio-restart";
29 miim_a_pins: mdio-pins {
35 pps_out_pins: pps-out-pins {
41 ptp_ext_pins: ptp-ext-pins {
[all …]
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
33 pinctrl-0 = <&usart0_pins>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-hi3798cv200-combphy.txt1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
[all …]
H A Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: CPSW Port's Interface Mode Selection PHY
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 The interface mode is selected by configuring the MII mode selection register(s)
20 +--------------+
21 +-------------------------------+ |SCM |
[all …]
/openbmc/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
181 enum pipe3_mode mode; member
206 enum pipe3_mode mode; member
212 .mode = PIPE3_MODE_USBSS,
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
238 .mode = PIPE3_MODE_SATA,
[all …]
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
42 pinctrl-names = "default";
[all …]
/openbmc/linux/drivers/phy/amlogic/
H A Dphy-meson-gxl-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson GXL and GXM USB2 PHY driver
15 #include <linux/phy/phy.h>
18 /* bits [31:27] are read-only */
66 /* bits [31:14] are read-only */
94 enum phy_mode mode; member
107 static int phy_meson_gxl_usb2_init(struct phy *phy) in phy_meson_gxl_usb2_init() argument
109 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb2_init()
112 ret = reset_control_reset(priv->reset); in phy_meson_gxl_usb2_init()
116 ret = clk_prepare_enable(priv->clk); in phy_meson_gxl_usb2_init()
[all …]
H A Dphy-meson-g12a-usb3-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic G12A USB3 + PCIE Combo PHY driver
15 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy.h>
60 struct phy *phy; member
61 unsigned int mode; member
79 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
80 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr()
84 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr()
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-snps-pcie3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
51 /* mode: RC, EP */
52 int mode; member
58 struct phy *phy; member
69 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
71 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
73 /* Actually We don't care EP/RC mode, but just record it */ in rockchip_p3phy_set_mode()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt1040rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t104xsi-pre.dtsi"
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
59 phy-handle = <&phy_sgmii_2>;
60 phy-connection-type = "sgmii";
64 phy_sgmii_2: ethernet-phy@3 {
68 /* VSC8514 QSGMII PHY */
[all …]
/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
19 #include <linux/phy/phy.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 64) : \
66 ((x) - 128))
67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrel.txt1 Micrel PHY properties.
7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
21 See the respective PHY datasheet for the mode values.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
27 than 50 MHz clock mode.
29 Note that this option in only needed for certain PHY revisions with a
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
[all …]
H A Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI DP83822 ethernet PHY
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
20 Specifications about the Ethernet PHY can be found at:
24 - $ref: ethernet-phy.yaml#
[all …]
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
[all …]

12345678910>>...42