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/openbmc/linux/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
/openbmc/phosphor-power/phosphor-regulators/src/
H A Dphase_fault_detection.hpp40 * Detects and logs redundant phase faults in a voltage regulator.
42 * A voltage regulator is sometimes called a "phase controller" because it
45 * A regulator may have redundant phases. If a redundant phase fails, the
47 * phase fault error should be logged warning the user that the regulator has
50 * The technique used to detect a phase fault varies depending on the regulator
54 * Phase fault detection is executed repeatedly based on a timer. A phase fault
58 * Phase faults are detected by executing actions.
74 * @param actions Actions that detect phase faults in the regulator.
75 * @param deviceID Unique ID of the device to use when detecting phase
100 * Executes the actions that detect phase faults in the regulator.
[all …]
H A Dphase_fault.hpp26 * Redundant phase fault type.
28 * A voltage regulator is sometimes called a "phase controller" because it
31 * A regulator may have redundant phases. If a redundant phase fails, the
33 * phase fault error should be logged warning the user that the regulator has
39 * N phase fault type.
47 * N+1 phase fault type.
49 * An "N+2" regulator has lost one redundant phase. The regulator is now at
60 * @param type phase fault type
81 * @param type phase fault type
82 * @return phase fault type name
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c55 * Desc: Execute the Read leveling phase by HW
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
108 phase = (reg >> REG_PHY_PHASE_OFFS) & in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
112 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
113 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
114 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
115 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
138 DEBUG_RL_S(", Phase: "); in ddr3_read_leveling_hw()
173 * Desc: Execute the Read leveling phase by SW
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
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/openbmc/linux/drivers/hwmon/pmbus/
H A Dmp2888.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
83 * Obtain resolution selector for total and phase current report and protection. in mp2888_current_sense_gain_and_resolution_get()
84 * 0: original resolution; 1: half resolution (in such case phase current value should in mp2888_current_sense_gain_and_resolution_get()
94 mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, int phase, u8 reg) in mp2888_read_phase() argument
98 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_phase()
102 if (!((phase + 1) % 2)) in mp2888_read_phase()
113 * - Rcs is the internal phase current sense resistor. This parameter depends on hardware in mp2888_read_phase()
116 * If phase current resolution bit is set to 1, READ_CSx value should be doubled. in mp2888_read_phase()
117 * Note, that current phase sensing, providing by the device is not accurate. This is in mp2888_read_phase()
128 mp2888_read_phases(struct i2c_client *client, struct mp2888_data *data, int page, int phase) in mp2888_read_phases() argument
[all …]
H A Dmp2975.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
130 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
133 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
197 int page, int phase, u8 reg) in mp2975_read_phase() argument
201 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
205 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
216 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
222 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
225 * case phase current is represented as the maximum between the value in mp2975_read_phase()
228 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
[all …]
H A Dmp2856.c113 mp2856_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2856_read_word_helper() argument
116 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2856_read_word_helper()
123 int phase, u8 reg) in mp2856_read_vout() argument
127 ret = mp2856_read_word_helper(client, page, phase, reg, in mp2856_read_vout()
141 int page, int phase, u8 reg) in mp2856_read_phase() argument
146 ret = pmbus_read_word_data(client, page, phase, reg); in mp2856_read_phase()
150 if (!((phase + 1) % MP2856_PAGE_NUM)) in mp2856_read_phase()
164 int page, int phase) in mp2856_read_phases() argument
169 switch (phase) { in mp2856_read_phases()
171 ret = mp2856_read_phase(client, data, page, phase, in mp2856_read_phases()
[all …]
/openbmc/phosphor-power/phosphor-regulators/test/
H A Dphase_fault_detection_tests.cpp201 // performing phase fault detection 10 times. The lambda allows us to in TEST_F()
206 // - 3 error messages for inability to detect phase faults in TEST_F()
207 // - 2 error messages for the N phase fault in TEST_F()
208 // - 2 error messages for the N+1 phase fault in TEST_F()
213 logError("Unable to detect phase faults in regulator vdd1")) in TEST_F()
217 logError("n phase fault detected in regulator vdd1: count=1")) in TEST_F()
221 logError("n phase fault detected in regulator vdd1: count=2")) in TEST_F()
225 logError("n+1 phase fault detected in regulator vdd1: count=1")) in TEST_F()
229 logError("n+1 phase fault detected in regulator vdd1: count=2")) in TEST_F()
234 // - N phase fault error should be logged once in TEST_F()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsamsung,exynos-dw-mshc.yaml54 - description: CIU clock phase shift value for tx mode
57 - description: CIU clock phase shift value for rx mode
61 The value of CUI clock phase shift value in transmit mode and CIU clock
62 phase shift value in receive mode for double data rate mode operation.
68 - description: CIU clock phase shift value for tx mode
71 - description: CIU clock phase shift value for rx mode
75 The value of CIU TX and RX clock phase shift value for HS400 mode
78 - valid value for tx phase shift and rx phase shift is 0 to 7.
79 - when CIU clock divider value is set to 3, all possible 8 phase shift
82 phase shift clocks should be 0.
[all …]
/openbmc/linux/drivers/clk/meson/
H A Dclk-phase.c11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
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/openbmc/linux/drivers/clk/sunxi/
H A Dclk-mod0.c173 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
179 value = readl(phase->reg); in mmc_get_phase()
180 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
215 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
266 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
267 value = readl(phase->reg); in mmc_set_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
269 value |= delay << phase->offset; in mmc_set_phase()
270 writel(value, phase->reg); in mmc_set_phase()
271 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_dccg.c53 int phase; in dccg21_update_dpp_dto() local
57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
58 * phase = ceiling(dpp_pipe_clk_mhz / 10) in dccg21_update_dpp_dto()
64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
70 /* phase > modulo result in screen corruption in dccg21_update_dpp_dto()
71 * ie phase = 30, mod = 29 for 4k@60 HDMI in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
78 * set phase to 10 if dpp isn't used to in dccg21_update_dpp_dto()
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/openbmc/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
/openbmc/phosphor-power/phosphor-regulators/docs/config_file/
H A Dphase_fault_detection.md5 Specifies how to detect and log redundant phase faults in a voltage regulator.
7 A voltage regulator is sometimes called a "phase controller" because it controls
10 A regulator may have redundant phases. If a redundant phase fails, the regulator
11 will continue to provide the desired output voltage. However, a phase fault
14 The technique used to detect a phase fault varies depending on the regulator
18 Phase fault detection is performed every 15 seconds. A phase fault must be
22 Phase faults are detected and logged by executing actions:
32 - Use the [log_phase_fault](log_phase_fault.md) action to log a phase fault
50 … array of strings | One or more comment lines describing the phase fault detection. …
63 "comments": ["Detect phase fault using I/O expander"],
[all …]
/openbmc/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_imem_ops.c19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
21 /* The network interface is only supported in the runtime phase. */ in ipc_imem_sys_wwan_open()
23 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id, in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
67 dev_dbg(ipc_imem->dev, "phase %s transmit", in ipc_imem_sys_wwan_transmit()
68 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_transmit()
146 enum ipc_phase phase; in ipc_imem_is_channel_active() local
148 /* Update the current operation phase. */ in ipc_imem_is_channel_active()
149 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
[all …]
H A Diosm_ipc_imem.c180 /* Use the TD update timer only in the runtime phase */ in ipc_imem_td_update_timer_start()
291 ipc_imem_phase_get_string(ipc_imem->phase), in ipc_imem_ipc_init_check()
404 /* Get the internal phase. */ in ipc_imem_ul_pipe_process()
468 /* Consider link power management in the runtime phase. */
487 /* Update & check the current operation phase. */ in ipc_imem_tq_startup_timer_cb()
540 return (ipc_imem->phase == IPC_P_RUN && in ipc_imem_get_exec_stage_buffered()
572 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_run_state_worker()
645 enum ipc_phase old_phase, phase; in ipc_imem_handle_irq() local
653 /* Get the internal phase. */ in ipc_imem_handle_irq()
654 old_phase = ipc_imem->phase; in ipc_imem_handle_irq()
[all …]
/openbmc/linux/include/linux/regulator/
H A Dda9121.h3 * DA9121 Single-channel dual-phase 10A buck converter
4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive)
5 * DA9217 Single-channel dual-phase 6A buck converter
6 * DA9122 Dual-channel single-phase 5A buck converter
7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive)
8 * DA9220 Dual-channel single-phase 3A buck converter
9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive)
/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Duncore-power.json25 "BriefDescription": "Phase Shed 0 Cycles",
29 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
33 "BriefDescription": "Phase Shed 1 Cycles",
37 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
41 "BriefDescription": "Phase Shed 2 Cycles",
45 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
49 "BriefDescription": "Phase Shed 3 Cycles",
53 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
103 "BriefDescription": "Memory Phase Shedding Cycles",
107 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
/openbmc/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c178 int phase; in dcss_scaler_gaussian_filter() local
183 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
184 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
185 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
225 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
232 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
237 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
239 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
243 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
264 * @use_5_taps: 0 for 7 taps per phase, 1 for 5 taps
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-power.json24 "BriefDescription": "Phase Shed 0 Cycles",
28 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
32 "BriefDescription": "Phase Shed 1 Cycles",
36 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
40 "BriefDescription": "Phase Shed 2 Cycles",
44 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
48 "BriefDescription": "Phase Shed 3 Cycles",
52 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
102 "BriefDescription": "Memory Phase Shedding Cycles",
106 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-power.json23 "BriefDescription": "Phase Shed 0 Cycles",
27 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
31 "BriefDescription": "Phase Shed 1 Cycles",
35 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
39 "BriefDescription": "Phase Shed 2 Cycles",
43 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
47 "BriefDescription": "Phase Shed 3 Cycles",
51 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
101 "BriefDescription": "Memory Phase Shedding Cycles",
105 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
/openbmc/linux/drivers/char/
H A Dppdev.c20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
404 pp->saved_state.phase = info->phase; in pp_do_ioctl()
406 info->phase = pp->state.phase; in pp_do_ioctl()
435 pp->state.phase = init_phase(mode); in pp_do_ioctl()
439 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
459 int phase; in pp_do_ioctl() local
461 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
464 /* FIXME: validate phase */ in pp_do_ioctl()
465 pp->state.phase = phase; in pp_do_ioctl()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Drealtek,otto-wdt.yaml15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
20 During this phase, pinging the WDT has no effect, and a reset is

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