| /openbmc/phosphor-power/phosphor-regulators/src/ |
| H A D | phase_fault_detection.hpp | 40 * Detects and logs redundant phase faults in a voltage regulator.
42 * A voltage regulator is sometimes called a "phase controller" because it
45 * A regulator may have redundant phases. If a redundant phase fails, the
47 * phase fault error should be logged warning the user that the regulator has
50 * The technique used to detect a phase fault varies depending on the regulator
54 * Phase fault detection is executed repeatedly based on a timer. A phase fault
58 * Phase faults are detected by executing actions.
74 * @param actions Actions that detect phase faults in the regulator.
75 * @param deviceID Unique ID of the device to use when detecting phase
100 * Executes the actions that detect phase faults in the regulator.
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| H A D | phase_fault.hpp | 26 * Redundant phase fault type.
28 * A voltage regulator is sometimes called a "phase controller" because it
31 * A regulator may have redundant phases. If a redundant phase fails, the
33 * phase fault error should be logged warning the user that the regulator has
39 * N phase fault type.
47 * N+1 phase fault type.
49 * An "N+2" regulator has lost one redundant phase. The regulator is now at
60 * @param type phase fault type
81 * @param type phase fault type
82 * @return phase fault type name
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| H A D | phase_fault_detection.cpp | 40 * Number of consecutive phase faults required to log an error. This provides
59 // Execute the actions to detect phase faults in execute()
62 // Check for any N or N+1 phase faults that were detected in execute()
75 "Unable to detect phase faults in regulator " + in execute()
100 // Check if the phase fault was detected in checkForPhaseFault()
103 // Phase fault not detected; reset consecutive fault count in checkForPhaseFault()
108 // Phase fault detected; increment consecutive fault count in checkForPhaseFault()
113 toString(faultType) + " phase fault detected in regulator " + in checkForPhaseFault()
119 // Log phase fault error and update ErrorHistory in checkForPhaseFault()
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| /openbmc/phosphor-power/phosphor-regulators/docs/ |
| H A D | phase_fault_monitoring.md | 1 # Phase Fault Monitoring
5 Some voltage regulators contain redundant phases. If a redundant phase fails,
7 lost, and the regulator may fail if another phase fails.
9 Voltage regulators can be monitored for redundant phase faults. If a fault is
13 application checks for redundant phase faults every 15 seconds.
15 A phase fault must be detected two consecutive times (15 seconds apart) before
19 A phase fault error will only be logged for a regulator once per system boot.
21 ## How phase fault detection is defined
23 Phase fault detection is defined for a voltage regulator using the
32 If a different type of error occurs while detecting phase faults in a regulator:
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| /openbmc/qemu/tests/tcg/multiarch/gdbstub/ |
| H A D | late-attach.py | 11 phase = gdb.parse_and_eval("phase").string()
14 phase = "start"
16 if phase == "start":
19 phase = gdb.parse_and_eval("phase").string()
20 report(phase == "sigwait", "{} == \"sigwait\"".format(phase))
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| /openbmc/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_read_leveling.c | 55 * Desc: Execute the Read leveling phase by HW
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
108 phase = (reg >> REG_PHY_PHASE_OFFS) & in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
112 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
113 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
114 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
115 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
138 DEBUG_RL_S(", Phase: "); in ddr3_read_leveling_hw()
173 * Desc: Execute the Read leveling phase by SW
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| H A D | ddr3_write_leveling.c | 58 * Desc: Execute Write leveling phase by HW
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
117 phase = in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
133 /* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */ in ddr3_write_leveling_hw()
145 DEBUG_WL_S(", Phase: "); in ddr3_write_leveling_hw()
186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
343 phase = in ddr3_wl_supplement()
351 [P] = phase; in ddr3_wl_supplement()
361 phase, delay); in ddr3_wl_supplement()
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| /openbmc/phosphor-power/phosphor-regulators/docs/config_file/ |
| H A D | phase_fault_detection.md | 5 Specifies how to detect and log redundant phase faults in a voltage regulator.
7 A voltage regulator is sometimes called a "phase controller" because it controls
10 A regulator may have redundant phases. If a redundant phase fails, the regulator
11 will continue to provide the desired output voltage. However, a phase fault
14 The technique used to detect a phase fault varies depending on the regulator
18 Phase fault detection is performed every 15 seconds. A phase fault must be
22 Phase faults are detected and logged by executing actions:
32 - Use the [log_phase_fault](log_phase_fault.md) action to log a phase fault
50 … array of strings | One or more comment lines describing the phase fault detection. …
63 "comments": ["Detect phase fault using I/O expander"],
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| H A D | log_phase_fault.md | 5 Logs a redundant phase fault error for a voltage regulator. This action should
12 - An "N+1" regulator has one redundant phase
14 A phase fault occurs when a phase stops functioning properly. The redundancy
17 The phase fault type indicates the level of redundancy remaining **after** the
22 | n+1 | An "N+2" regulator has lost one redundant phase. The regulator is now at redundancy level …
33 | type | yes | string | Phase fault type. Specify one of the following: "n+1", "n". |
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| /openbmc/phosphor-power/phosphor-regulators/test/ |
| H A D | phase_fault_detection_tests.cpp | 201 // performing phase fault detection 10 times. The lambda allows us to in TEST_F()
206 // - 3 error messages for inability to detect phase faults in TEST_F()
207 // - 2 error messages for the N phase fault in TEST_F()
208 // - 2 error messages for the N+1 phase fault in TEST_F()
213 logError("Unable to detect phase faults in regulator vdd1")) in TEST_F()
217 logError("n phase fault detected in regulator vdd1: count=1")) in TEST_F()
221 logError("n phase fault detected in regulator vdd1: count=2")) in TEST_F()
225 logError("n+1 phase fault detected in regulator vdd1: count=1")) in TEST_F()
229 logError("n+1 phase fault detected in regulator vdd1: count=2")) in TEST_F()
234 // - N phase fault error should be logged once in TEST_F()
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| /openbmc/phosphor-power/phosphor-regulators/src/actions/ |
| H A D | log_phase_fault_action.hpp | 30 * Logs a redundant phase fault error for a voltage regulator.
48 * @param type phase fault type
55 * Adds the phase fault to the set that have been detected.
67 * Returns the phase fault type.
69 * @return phase fault type
88 * Phase fault type.
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| /openbmc/qemu/docs/devel/ |
| H A D | reset.rst | 109 Multi-phase mechanism
114 The resettable interface uses a multi-phase system to relieve objects and
124 1. The **enter** phase is executed when the object enters reset. It resets only
129 2. The **hold** phase is executed for entry into reset, once every object in the
130 group which is being reset has had its *enter* phase executed. At this point
133 3. The **exit** phase is executed when the object leaves the reset state.
142 The *exit* phase is executed only when the last reset operation ends. Therefore
148 the 'exit' phase and this sequencing makes sure no outstanding DMA request
164 phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and
181 /* call parent class enter phase */
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| /openbmc/qemu/include/hw/ |
| H A D | resettable.h | 66 * The phase methods are guaranteed to only only ever be called once
70 * before eventually reset is deasserted and the 'exit' phase is called.
79 * @phases.enter: This phase is called when the object enters reset. It
85 * @phases.hold: This phase is called for entry into reset, once every object
89 * @phases.exit: This phase is called when the object leaves the reset state.
119 /* Phase methods */
138 * phase handler for this object.
139 * @exit_phase_in_progress: true if we are currently in the exit phase
211 * a hold phase method. Calling this during enter or exit phase is an error.
229 * Each phase is overridden only if the new one is not NULL allowing to
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| /openbmc/qemu/docs/devel/migration/ |
| H A D | vfio.rst | 10 Migration of VFIO devices consists of two phases: the optional pre-copy phase,
11 and the stop-and-copy phase. The pre-copy phase is iterative and allows to
13 transferred. The iterative pre-copy phase of migration allows for the guest to
65 vendor driver during iterative pre-copy phase.
142 phase. So, a page marked as dirty will be copied to the destination in both
143 phases. Copying dirty pages in pre-copy phase helps QEMU to predict if it can
144 achieve its downtime tolerances. If QEMU during pre-copy phase keeps finding
145 dirty pages continuously, then it understands that even in stop-and-copy phase,
149 which disables querying the dirty bitmap during pre-copy phase. If it is set to
150 off, all dirty pages will be copied to the destination in stop-and-copy phase
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| /openbmc/qemu/include/system/ |
| H A D | reset.h | 41 * they were added, using the three-phase Resettable protocol,
42 * so first all objects go through the enter phase, then all objects
43 * go through the hold phase, and then finally all go through the
44 * exit phase.
47 * resettable objects from within any of the reset phase methods of @obj.
74 * Functions registered with this API are called in the 'hold' phase
75 * of the 3-phase reset.
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| /openbmc/u-boot/drivers/fpga/ |
| H A D | socfpga_gen5.c | 80 /* Put FPGA into reset phase */ in fpgamgr_program_init()
83 /* (1) wait until FPGA enter reset phase */ in fpgamgr_program_init()
95 /* Release FPGA from reset phase */ in fpgamgr_program_init()
98 /* (2) wait until FPGA enter configuration phase */ in fpgamgr_program_init()
153 /* Ensure the FPGA entering init phase */
158 /* Additional clocks for the CB to enter initialization phase */ in fpgamgr_program_poll_initphase()
162 /* (4) wait until FPGA enter init phase or user mode */ in fpgamgr_program_poll_initphase()
182 /* Additional clocks for the CB to exit initialization phase */ in fpgamgr_program_poll_usermode()
242 /* Ensure the FPGA entering init phase */ in socfpga_load()
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| /openbmc/qemu/hw/core/ |
| H A D | resettable.c | 20 * Function executing a phase recursively in a resettable object and its
29 * True if we are currently in reset enter phase.
32 * count the number of exit phase we are in.
103 /* exit phase has to finish properly before entering back in reset */ in resettable_phase_enter()
131 /* execute enter phase for the object if needed */ in resettable_phase_enter()
149 /* exit phase has to finish properly before entering back in reset */ in resettable_phase_hold()
157 /* exec hold phase */ in resettable_phase_hold()
177 /* exit_phase_in_progress ensures this phase is 'atomic' */ in resettable_phase_exit()
213 * Ensure we do not change parent when in enter or exit phase. in resettable_change_parent()
233 * hold phase is not pending. in resettable_change_parent()
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| /openbmc/u-boot/arch/x86/cpu/intel_common/ |
| H A D | me_status.c | 51 [ME_GMES_PHASE_ROM] = "ROM Phase",
52 [ME_GMES_PHASE_BUP] = "BUP Phase",
53 [ME_GMES_PHASE_UKERNEL] = "uKernel Phase",
160 debug("ME: Progress Phase : %s\n", in _intel_me_status()
165 debug("ME: Progress Phase State : "); in _intel_me_status()
167 case ME_GMES_PHASE_ROM: /* ROM Phase */ in _intel_me_status()
171 case ME_GMES_PHASE_BUP: /* Bringup Phase */ in _intel_me_status()
180 case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ in _intel_me_status()
190 case ME_GMES_PHASE_HOST: /* Host Communication Phase */ in _intel_me_status()
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| /openbmc/bmcweb/redfish-core/schema/dmtf/csdl/ |
| H A D | Circuit_v1.xml | 159 …<Annotation Term="OData.Description" String="Single-phase / 3-wire (Line1, Neutral, Protective Ear…
160 … Term="OData.LongDescription" String="This value shall represent a single-phase / 3-wire (Line1, N…
163 …<Annotation Term="OData.Description" String="Two-phase / 3-wire (Line1, Line2, Protective Earth)."…
164 …<Annotation Term="OData.LongDescription" String="This value shall represent a two-phase / 3-wire (…
167 …<Annotation Term="OData.Description" String="Single or two-phase / 3-wire (Line1, Line2 or Neutral…
168 …phase / 3-wire (Line1, Line2 or Neutral, Protective Earth) wiring. This value shall be used when …
171 …<Annotation Term="OData.Description" String="Two-phase / 4-wire (Line1, Line2, Neutral, Protective…
172 …<Annotation Term="OData.LongDescription" String="This value shall represent a two-phase / 4-wire (…
175 …<Annotation Term="OData.Description" String="Three-phase / 4-wire (Line1, Line2, Line3, Protective…
176 …<Annotation Term="OData.LongDescription" String="This value shall represent a three-phase / 4-wire…
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| /openbmc/openbmc/poky/meta/recipes-connectivity/openssl/openssl/ |
| H A D | 0001-Added-handshake-history-reporting-when-test-fails.patch | 69 +const char *handshake_connect_phase_name(connect_phase_t phase)
72 + (int)phase);
88 + connect_phase_t phase,
106 + new_entry->phase = phase;
126 -/* The status for each connection phase. */
181 + phase, status, server.status, client.status,
192 + phase, status, server.status, client.status,
235 +/* The status for each connection phase. */
259 + connect_phase_t phase;
298 +const char *handshake_connect_phase_name(connect_phase_t phase);
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | ast2600a1-evb.dts | 11 timing-phase = <0x000700bf>;
15 timing-phase = <0x01084747>;
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| /openbmc/qemu/scripts/coccinelle/ |
| H A D | reset-type.cocci | 1 // Convert device code using three-phase reset to add a ResetType
16 // implementations of the hold and exit phase methods" it includes
101 identifier phase;
104 - rc->phases.phase(obj)@p
105 + rc->phases.phase(obj, RESET_TYPE_COLD)
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| /openbmc/u-boot/drivers/usb/dwc3/ |
| H A D | ep0.c | 39 return "Setup Phase"; in dwc3_ep0_state_string()
41 return "Data Phase"; in dwc3_ep0_state_string()
43 return "Status Phase"; in dwc3_ep0_state_string()
148 * In case gadget driver asked us to delay the STATUS phase, in __dwc3_gadget_ep0_queue()
167 * Unfortunately we have uncovered a limitation wrt the Data Phase. in __dwc3_gadget_ep0_queue()
171 * miss situations where the host starts another SETUP phase instead of in __dwc3_gadget_ep0_queue()
172 * the DATA phase. Such cases happen at least on TD.7.6 of the Link in __dwc3_gadget_ep0_queue()
180 * it tells us to start Data Phase right away. It also mentions that if in __dwc3_gadget_ep0_queue()
181 * we receive a SETUP phase instead of the DATA phase, core will issue in __dwc3_gadget_ep0_queue()
182 * XferComplete for the DATA phase, before actually initiating it in in __dwc3_gadget_ep0_queue()
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| /openbmc/u-boot/drivers/usb/emul/ |
| H A D | sandbox_flash.c | 58 enum cmd_phase phase; member
292 priv->phase = priv->transfer_len ? PHASE_DATA : PHASE_STATUS; in handle_ufi_command()
304 debug("%s: dev=%s, pipe=%lx, ep=%x, len=%x, phase=%d\n", __func__, in sandbox_flash_bulk()
305 dev->name, pipe, ep, len, priv->phase); in sandbox_flash_bulk()
308 switch (priv->phase) { in sandbox_flash_bulk()
331 switch (priv->phase) { in sandbox_flash_bulk()
343 priv->phase = PHASE_STATUS; in sandbox_flash_bulk()
348 priv->phase = PHASE_STATUS; in sandbox_flash_bulk()
356 priv->phase = PHASE_START; in sandbox_flash_bulk()
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| /openbmc/u-boot/drivers/ddr/altera/ |
| H A D | sequencer.c | 285 static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase) in scc_mgr_set_dqdqs_output_phase() argument
287 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase); in scc_mgr_set_dqdqs_output_phase()
295 static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase) in scc_mgr_set_dqs_en_phase() argument
297 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase); in scc_mgr_set_dqs_en_phase()
391 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) in scc_mgr_set_dqs_en_phase_all_ranks() argument
396 * keeps different phase settings per shadow reg, and it's in scc_mgr_set_dqs_en_phase_all_ranks()
402 read_group, phase, 0); in scc_mgr_set_dqs_en_phase_all_ranks()
406 u32 phase) in scc_mgr_set_dqdqs_output_phase_all_ranks() argument
411 * keeps different phase settings per shadow reg, and it's in scc_mgr_set_dqdqs_output_phase_all_ranks()
417 write_group, phase, 0); in scc_mgr_set_dqdqs_output_phase_all_ranks()
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