285 static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase)  in scc_mgr_set_dqdqs_output_phase()  argument
287 	scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);  in scc_mgr_set_dqdqs_output_phase()
295 static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase)  in scc_mgr_set_dqs_en_phase()  argument
297 	scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);  in scc_mgr_set_dqs_en_phase()
391 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)  in scc_mgr_set_dqs_en_phase_all_ranks()  argument
396 	 * keeps different phase settings per shadow reg, and it's  in scc_mgr_set_dqs_en_phase_all_ranks()
402 			      read_group, phase, 0);  in scc_mgr_set_dqs_en_phase_all_ranks()
406 						     u32 phase)  in scc_mgr_set_dqdqs_output_phase_all_ranks()  argument
411 	 * keeps different phase settings per shadow reg, and it's  in scc_mgr_set_dqdqs_output_phase_all_ranks()
417 			      write_group, phase, 0);  in scc_mgr_set_dqdqs_output_phase_all_ranks()
1546  * sdr_find_phase_delay() - Find DQS enable phase or delay
1547  * @working:	If 1, look for working phase/delay, if 0, look for non-working
1548  * @delay:	If 1, look for delay, if 0, look for phase
1552  * @pd:		DQS Phase/Delay Iterator
1554  * Find working or non-working DQS enable phase setting.
1584  * sdr_find_phase() - Find DQS enable phase
1585  * @working:	If 1, look for working phase, if 0, look for non-working phase
1589  * @p:		DQS Phase Iterator
1591  * Find working or non-working DQS enable phase setting.
1620  * sdr_working_phase() - Find working DQS enable phase
1624  * @p:		DQS Phase Iterator
1627  * Find working DQS enable phase setting.
1654  * sdr_backup_phase() - Find DQS enable backup phase
1657  * @p:		DQS Phase Iterator
1659  * Find DQS enable backup phase setting.
1666 	/* Special case code for backing up a phase */  in sdr_backup_phase()
1701  * sdr_nonworking_phase() - Find non-working DQS enable phase
1704  * @p:		DQS Phase Iterator
1707  * Find non-working DQS enable phase setting.
1820 	/* Step 0: Determine number of delay taps for each phase tap. */  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
1827 	/* Step 2: Find first working phase, increment in ptaps. */  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
1836 	 * If d is 0 then the working window covers a phase tap and we can  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
1848 		 * Step 4a: go forward from working phase to non working  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
1849 		 * phase, increment in ptaps.  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
1857 		/* Special case code for backing up a phase */  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
1904 	/* Special case code for backing up a phase */  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
1908 		debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
1912 		debug_cond(DLEVEL >= 2, "%s:%d backedup phase only: p=%u",  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
2018  * search_left_edge() - Find left edge of DQ/DQS working phase
2025  * @left_edge:		Left edge of the DQ/DQS phase
2026  * @right_edge:		Right edge of the DQ/DQS phase
2029  * Find left edge of DQ/DQS working phase.
2127  * search_right_edge() - Find right edge of DQ/DQS working phase
2132  * @start_dqs:		DQS start phase
2133  * @start_dqs_en:	DQS enable start phase
2135  * @left_edge:		Left edge of the DQ/DQS phase
2136  * @right_edge:		Right edge of the DQ/DQS phase
2139  * Find right edge of DQ/DQS working phase.
2258  * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2260  * @left_edge:		Left edge of the DQ/DQS phase
2261  * @right_edge:		Right edge of the DQ/DQS phase
2262  * @mid_min:		Best DQ/DQS phase middle setting
2264  * Find index and value of the middle of the DQ/DQS working phase.
2302  * @left_edge:		Left edge of the DQ/DQS phase
2303  * @right_edge:		Right edge of the DQ/DQS phase
2304  * @mid_min:		Adjusted DQ/DQS phase middle setting
2305  * @orig_mid_min:	Original DQ/DQS phase middle setting
2306  * @min_index:		DQ/DQS phase middle setting index
2525  * @phase:	DQ/DQS phase
2532 						 const u32 phase)  in rw_mgr_mem_calibrate_guaranteed_write()  argument
2536 	/* Set a particular DQ/DQS phase. */  in rw_mgr_mem_calibrate_guaranteed_write()
2537 	scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);  in rw_mgr_mem_calibrate_guaranteed_write()
2540 		   __func__, __LINE__, rw_group, phase);  in rw_mgr_mem_calibrate_guaranteed_write()
2545 	 * current DQDQS phase.  in rw_mgr_mem_calibrate_guaranteed_write()
2560 			   __func__, __LINE__, rw_group, phase);  in rw_mgr_mem_calibrate_guaranteed_write()
2678  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2679  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2699 	/* USER Determine number of delay taps for each phase tap. */  in rw_mgr_mem_calibrate_vfifo()
3220 		 * Set output phase alignment settings appropriate for  in mem_skip_calibrate()
3356 		 * Zero all delay chain/phase settings for all  in mem_calibrate()