58  * Desc:     Execute Write leveling phase by HW
66 	u32 reg, phase, delay, cs, pup;  in ddr3_write_leveling_hw()  local
117 					phase =  in ddr3_write_leveling_hw()
121 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_hw()
133 				/* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */  in ddr3_write_leveling_hw()
145 					DEBUG_WL_S(", Phase: ");  in ddr3_write_leveling_hw()
186 	u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset;  in ddr3_wl_supplement()  local
343 							phase =  in ddr3_wl_supplement()
351 							    [P] = phase;  in ddr3_wl_supplement()
361 							     phase, delay);  in ddr3_wl_supplement()
364 							phase =  in ddr3_wl_supplement()
373 							if ((phase == 0)  in ddr3_wl_supplement()
374 							    || ((phase == 1)  in ddr3_wl_supplement()
380 							phase = 0x0;  in ddr3_wl_supplement()
384 							    [P] = phase;  in ddr3_wl_supplement()
392 							     phase, delay);  in ddr3_wl_supplement()
394 						/* Stop condition for ECC phase */  in ddr3_wl_supplement()
437 				phase =  in ddr3_wl_supplement()
440 				if (phase > dram_info->wl_max_phase)  in ddr3_wl_supplement()
441 					dram_info->wl_max_phase = phase;  in ddr3_wl_supplement()
442 				if (phase < dram_info->wl_min_phase)  in ddr3_wl_supplement()
443 					dram_info->wl_min_phase = phase;  in ddr3_wl_supplement()
466  * Desc:     Execute Write leveling phase by HW
474 	u32 reg, phase, delay, cs, pup, pup_num;  in ddr3_write_leveling_hw_reg_dimm()  local
540 					phase =  in ddr3_write_leveling_hw_reg_dimm()
544 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_hw_reg_dimm()
546 					if ((phase == 1) && (delay >= 0x1D)) {  in ddr3_write_leveling_hw_reg_dimm()
570 				 * cs,PUP,Phase,Delay  in ddr3_write_leveling_hw_reg_dimm()
581 					DEBUG_WL_S(", Phase: ");  in ddr3_write_leveling_hw_reg_dimm()
651  * Desc:     Execute Write leveling phase by SW
875  * Desc:     Execute Write leveling phase by SW
1127 	u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup,  in ddr3_write_leveling_single_cs()  local
1183 	/* Broadcast to all PUPs: Reset DQS phase, reset leveling delay */  in ddr3_write_leveling_single_cs()
1213 	if (!ratio_2to1) /* Different phase options for 2:1 or 1:1 modes */  in ddr3_write_leveling_single_cs()
1221 	for (phase = 0; phase < phaseMax; phase++) {  in ddr3_write_leveling_single_cs()
1223 			/*  Broadcast to all PUPs: DQS phase,leveling delay */  in ddr3_write_leveling_single_cs()
1224 			ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, phase,  in ddr3_write_leveling_single_cs()
1229 			DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge: Phase = ");  in ddr3_write_leveling_single_cs()
1230 			DEBUG_WL_FULL_D((u32) phase, 1);  in ddr3_write_leveling_single_cs()
1267 					/* Update phase to PUP */  in ddr3_write_leveling_single_cs()
1268 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_single_cs()
1292 				phase = phaseMax;  in ddr3_write_leveling_single_cs()
1299 	/* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */  in ddr3_write_leveling_single_cs()
1304 		DEBUG_WL_S(", Phase: ");  in ddr3_write_leveling_single_cs()
1321 		phase = dram_info->wl_val[cs][pup][P];  in ddr3_write_leveling_single_cs()
1323 		ddr3_write_pup_reg(PUP_WL_MODE, cs, pup_num, phase, delay);  in ddr3_write_leveling_single_cs()