Home
last modified time | relevance | path

Searched +full:per +full:- +full:phy (Results 1 – 25 of 1023) sorted by relevance

12345678910>>...41

/openbmc/linux/drivers/scsi/mpt3sas/
H A Dmpt3sas_transport.c5 * Copyright (C) 2012-2014 LSI Corporation
6 * Copyright (C) 2013-2014 Avago Technologies
7 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
64 * _transport_get_port_id_by_sas_phy - get zone's port id that Phy belong to
65 * @phy: sas_phy object
70 _transport_get_port_id_by_sas_phy(struct sas_phy *phy) in _transport_get_port_id_by_sas_phy() argument
73 struct hba_port *port = phy->hostdata; in _transport_get_port_id_by_sas_phy()
76 port_id = port->port_id; in _transport_get_port_id_by_sas_phy()
[all …]
/openbmc/linux/include/uapi/linux/
H A Datmioc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* atmioc.h - ranges for ATM-related ioctl numbers */
4 /* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
8 * See https://icawww1.epfl.ch/linux-atm/magic.html for the complete list of
19 #define ATMIOC_PHYCOM 0x00 /* PHY device common ioctls, globally unique */
21 #define ATMIOC_PHYTYP 0x10 /* PHY dev type ioctls, unique per PHY type */
23 #define ATMIOC_PHYPRV 0x30 /* PHY dev private ioctls, unique per driver */
27 #define ATMIOC_SARPRV 0x60 /* SAR dev private ioctls, unique per driver */
31 #define ATMIOC_BACKEND 0x90 /* ATM generic backend ioctls, u. per backend */
33 /* 0xb0-0xbf: Reserved for future use */
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dbinding.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2020, 2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
17 * struct iwl_binding_cmd_v1 - configuring bindings
24 * @phy: PHY id and color which belongs to the binding,
33 __le32 phy; member
37 * struct iwl_binding_cmd - configuring bindings
44 * @phy: PHY id and color which belongs to the binding
54 __le32 phy; member
[all …]
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dk3-am654-ddrss.txt5 Synopys DDR controller, Synopsis DDR phy and wrapper logic to
9 configuring the DDRSS registers and using the buitin PHY
15 --------------------
16 - compatible: Shall be: "ti,am654-ddrss"
17 - reg-names ss - Map the sub system wrapper logic region
18 ctl - Map the controller region
19 phy - Map the PHY region
20 - reg: Contains the register map per reg-names.
21 - power-domains: Should contain a phandle to a PM domain provider node
23 value. This property is as per the binding,
[all …]
/openbmc/linux/include/linux/phy/
H A Dphy-lvds.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
18 * @is_slave: Boolean, true if the phy is a slave
20 * phy to support dual link transmission,
21 * otherwise a regular phy or a master phy.
23 * This structure is used to represent the configuration state of a LVDS phy.
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
16 * +---------------+ +---------------+ +---------------+
18 * +---------------+ +---------------+ +---------------+
24 * +---------------+ +---------------+
26 * +---------------+ +---------------+
37 * - 823.4375 MHz
38 * - 783.36 MHz
39 * - 796.875 MHz
40 * - 816 MHz
41 * - 830.078125 MHz
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
21 <1> : Attila PHY
22 <2> : Intelli PHY
24 - device-handle : phandle to a "lpddr2" node representing the memory part
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-pcie-phy.txt1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
[all …]
H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8MQ USB3 PHY
10 - Li Jun <jun.li@nxp.com>
15 - fsl,imx8mq-usb-phy
16 - fsl,imx8mp-usb-phy
21 "#phy-cells":
27 clock-names:
[all …]
/openbmc/linux/drivers/staging/media/omap4iss/
H A Diss_csiphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * TI OMAP4 ISS V4L2 Driver - CSI PHY module
14 #include "../../../../arch/arm/mach-omap2/control.h"
21 * csiphy_lanes_config - Configuration of CSIPHY lanes.
24 * Called with phy->mutex taken.
26 static void csiphy_lanes_config(struct iss_csiphy *phy) in csiphy_lanes_config() argument
31 reg = iss_reg_read(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG); in csiphy_lanes_config()
33 for (i = 0; i < phy->max_data_lanes; i++) { in csiphy_lanes_config()
36 reg |= (phy->lanes.data[i].pol ? in csiphy_lanes_config()
38 reg |= (phy->lanes.data[i].pos << in csiphy_lanes_config()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
[all …]
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
16 MDIO bus must have a list of child nodes, one per device on the
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dmain.h48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
145 ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
152 * gmode_user: user config gmode, operating band->gmode is different.
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp.h"
66 /* set of registers with offsets different per-PHY */
169 /* struct qmp_phy_cfg - per-PHY initialization config */
174 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
199 * struct qmp_phy - per-lane phy descriptor
201 * @phy: generic phy
202 * @cfg: phy specific configuration
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Ddebugfs.c1 // SPDX-License-Identifier: ISC
31 dev->ibf = !!val; in mt7996_implicit_txbf_set()
41 *val = dev->ibf; in mt7996_implicit_txbf_get()
54 struct mt7996_phy *phy = file->private_data; in mt7996_sys_recovery_set() local
55 struct mt7996_dev *dev = phy->dev; in mt7996_sys_recovery_set()
56 bool band = phy->mt76->band_idx; in mt7996_sys_recovery_set()
62 return -EINVAL; in mt7996_sys_recovery_set()
65 return -EFAULT; in mt7996_sys_recovery_set()
67 if (count && buf[count - 1] == '\n') in mt7996_sys_recovery_set()
68 buf[count - 1] = '\0'; in mt7996_sys_recovery_set()
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-h3-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun6i-rtc.h>
44 #include <dt-bindings/clock/sun8i-de2.h>
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 interrupt-parent = <&gic>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dphy-stm32-usbphyc.txt1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
19 Phy provider node
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
118 /* select phy interface in top control domain */ in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
146 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dspear13xx-pcie.txt4 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
8 - compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
9 - phys : phandle to PHY node associated with PCIe controller
10 - phy-names : must be "pcie-phy"
11 - All other definitions as per generic PCI bindings
14 - st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx35.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include "imx35-pinfunc.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1136jf-s";
48 avic: avic-interrupt-controller@68000000 {
49 compatible = "fsl,imx35-avic", "fsl,avic";
[all …]
/openbmc/linux/Documentation/networking/dsa/
H A Ddsa.rst22 An Ethernet switch typically comprises multiple front-panel ports and one
27 gateways, or even top-of-rack switches. This host Ethernet controller will
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
57 - the "cpu" port is the Ethernet switch facing side of the management
61 - the "dsa" port(s) are just conduits between two or more switches, and as such
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dxmit.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 __le16 phy_ctl; /* PHY TX control */
70 /* PHY TX control word */
94 u8 phy_stat; /* PHY TX status */
134 __le16 phy_status0; /* PHY RX Status 0 */
135 __u8 jssi; /* PHY RX Status 1: JSSI */
136 __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
137 PAD_BYTES(2); /* PHY RX Status 2 */
138 __le16 phy_status3; /* PHY RX Status 3 */
145 /* PHY RX Status 0 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dti,keystone-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Quadros <rogerq@kernel.org>
15 - enum:
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
22 '#address-cells':
25 '#size-cells':
[all …]

12345678910>>...41