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/openbmc/linux/drivers/firmware/efi/
H A Dcper.c1 // SPDX-License-Identifier: GPL-2.0
32 * multiple boot may co-exist in ERST.
73 * cper_print_bits - print strings for set bits
103 len += scnprintf(buf+len, sizeof(buf)-len, ", %s", str); in cper_print_bits()
127 "micro-architectural error",
147 if (proc->validation_bits & CPER_PROC_VALID_TYPE) in cper_print_proc_generic()
148 printk("%s""processor_type: %d, %s\n", pfx, proc->proc_type, in cper_print_proc_generic()
149 proc->proc_type < ARRAY_SIZE(proc_type_strs) ? in cper_print_proc_generic()
150 proc_type_strs[proc->proc_type] : "unknown"); in cper_print_proc_generic()
151 if (proc->validation_bits & CPER_PROC_VALID_ISA) in cper_print_proc_generic()
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpcie-iproc-bcma.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
15 #include "pcie-iproc.h"
21 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in bcma_pcie2_fixup_class()
28 struct iproc_pcie *pcie = dev->sysdata; in iproc_bcma_pcie_map_irq() local
29 struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); in iproc_bcma_pcie_map_irq()
36 struct device *dev = &bdev->dev; in iproc_bcma_pcie_probe()
37 struct iproc_pcie *pcie; in iproc_bcma_pcie_probe() local
41 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_bcma_pcie_probe()
43 return -ENOMEM; in iproc_bcma_pcie_probe()
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpcie_layerscape.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) in dbi_readl() argument
27 return in_le32(pcie->dbi + offset); in dbi_readl()
30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, in dbi_writel() argument
33 out_le32(pcie->dbi + offset, value); in dbi_writel()
36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) in ctrl_readl() argument
38 if (pcie->big_endian) in ctrl_readl()
39 return in_be32(pcie->ctrl + offset); in ctrl_readl()
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H A Dpci_mvebu.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell MVEBU SoCs
5 * Based on Barebox drivers/pci/pci-mvebu.c
7 * Ported to U-Boot by:
14 #include <dm/device-internal.h>
27 /* PCIe unit register offsets */
38 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
71 struct resource mem; member
84 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
85 * into SoCs address space. Each controller will map 128M of MEM
[all …]
H A Dpcie_dw_mvebu.c1 // SPDX-License-Identifier: GPL-2.0+
8 * - drivers/pci/pcie_imx.c
9 * - drivers/pci/pci_mvebu.c
10 * - drivers/pci/pcie_xilinx.c
17 #include <asm-generic/gpio.h>
97 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
103 * @first_busno: This driver supports multiple PCIe controllers.
104 * first_busno stores the bus number of the PCIe root-port
105 * number which may vary depending on the PCIe setup
114 /* IO and MEM PCI regions */
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dmvebu-pci.txt1 * Marvell EBU PCIe interfaces
5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
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H A Dsifive,fu740-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive FU740 PCIe host controller
10 SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
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H A Dcdns,cdns-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-ep.yaml#
17 const: cdns,cdns-pcie-ep
22 reg-names:
24 - const: reg
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H A Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: cdns-pcie-ep.yaml#
19 - const: ti,j721e-pcie-ep
20 - description: PCIe EP controller in AM64
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H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Endpoint
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
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/openbmc/u-boot/arch/arm/dts/
H A Darmada-xp-mv78460.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
64 #address-cells = <1>;
65 #size-cells = <0>;
66 enable-method = "marvell,armada-xp-smp";
70 compatible = "marvell,sheeva-v7";
73 clock-latency = <1000000>;
78 compatible = "marvell,sheeva-v7";
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H A Darmada-xp-mv78260.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 enable-method = "marvell,armada-xp-smp";
69 compatible = "marvell,sheeva-v7";
72 clock-latency = <1000000>;
77 compatible = "marvell,sheeva-v7";
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H A Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
36 pciec: pcie {
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H A Darmada-xp-mv78230.dtsi6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
50 #include "armada-xp.dtsi"
54 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 enable-method = "marvell,armada-xp-smp";
68 compatible = "marvell,sheeva-v7";
71 clock-latency = <1000000>;
76 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-380.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-385.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
36 pciec: pcie {
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H A Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-380.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
31 internal-regs {
33 compatible = "marvell,mv88f6810-pinctrl";
[all …]
/openbmc/qemu/hw/pci-host/
H A Ddesignware.c4 * Designware PCIe IP block emulation
29 #include "hw/qdev-properties.h"
32 #include "hw/pci-host/designware.h"
66 k->max_dev = 1; in designware_pcie_root_bus_class_init()
73 return DESIGNWARE_PCIE_HOST(bus->parent); in designware_pcie_root_to_host()
84 * AHB/AXI bus like any other PCI-device-initiated DMA read. in designware_pcie_root_msi_read()
86 * well-behaved guests won't ever ask a PCI device to DMA from in designware_pcie_root_msi_read()
99 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; in designware_pcie_root_msi_write()
101 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { in designware_pcie_root_msi_write()
102 qemu_set_irq(host->pci.msi, 1); in designware_pcie_root_msi_write()
[all …]
/openbmc/linux/arch/powerpc/sysdev/
H A Dfsl_pci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC83xx/85xx/86xx PCI/PCIE support routing.
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
11 * Roy Zang <tie-fei.zang@freescale.com>
12 * MPC83xx PCI-Express support:
34 #include <asm/pci-bridge.h>
35 #include <asm/ppc-pci.h>
39 #include <asm/ppc-opcode.h>
51 /* if we aren't a PCIe don't bother */ in quirk_fsl_pcie_early()
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/openbmc/qemu/docs/system/devices/
H A Dcxl.rst20 CXL elements are built upon an equivalent PCIe devices.
24 * Most conventional PCIe interfaces
26 - Configuration space access
27 - BAR mapped memory accesses used for registers and mailboxes.
28 - MSI/MSI-X
29 - AER
30 - DOE mailboxes
31 - IDE
32 - Many other PCI express defined interfaces..
36 - Equivalent of accessing DRAM / NVDIMMs. Any access / feature
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dturris1x.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
41 gpio-controller@18 {
45 #gpio-cells = <2>;
46 gpio-controller;
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/openbmc/qemu/tests/qtest/
H A Dcxl-test.c5 * See the COPYING file in the top-level directory.
9 #include "libqtest-single.h"
12 "-machine q35,cxl=on " \
13 "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
14 "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G "
17 "-machine q35,cxl=on " \
18 "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
19 "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
20 "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
23 "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
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