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/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DPCIeDevice.v1_20_0.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
37 "description": "The CXL-specific properties of a PCIe device.",
38 "longDescription": "This type shall contain CXL-specific properties of a PCIe device.",
40 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
55 … "description": "An array of the CXL specification revisions supported by this device.",
66 …his property shall contain an array of the CXL specification revisions that this device supports.",
[all …]
H A DPCIeFunction.v1_6_0.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
69 "InputDeviceController": "An input device controller.",
75 "NonEssentialInstrumentation": "A non-essential instrumentation.",
83 "UnclassifiedDevice": "An unclassified device.",
90 "PCIe",
94 "CXL": "A PCIe function supporting CXL extensions.",
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DPCIeDevice.v1_20_0.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
37 "description": "The CXL-specific properties of a PCIe device.",
38 "longDescription": "This type shall contain CXL-specific properties of a PCIe device.",
40 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
55 … "description": "An array of the CXL specification revisions supported by this device.",
66 …his property shall contain an array of the CXL specification revisions that this device supports.",
[all …]
H A DPCIeFunction.v1_6_0.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
28 "description": "The available OEM-specific actions for this resource.",
29 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
69 "InputDeviceController": "An input device controller.",
75 "NonEssentialInstrumentation": "A non-essential instrumentation.",
83 "UnclassifiedDevice": "An unclassified device.",
90 "PCIe",
94 "CXL": "A PCIe function supporting CXL extensions.",
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpcie_xilinx.c1 // SPDX-License-Identifier: GPL-2.0
15 * struct xilinx_pcie - Xilinx PCIe controller state
27 * pcie_xilinx_link_up() - Check whether the PCIe link is up
28 * @pcie: Pointer to the PCI controller state
30 * Checks whether the PCIe link for the given device is up or down.
34 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) in pcie_xilinx_link_up() argument
36 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); in pcie_xilinx_link_up()
42 * pcie_xilinx_config_address() - Calculate the address of a config access
44 * @bdf: Identifies the PCIe device to access
45 * @offset: The offset into the device's configuration space
[all …]
H A Dpci-aardvark.c20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
31 #include <asm-generic/gpio.h>
34 /* PCIe core registers */
102 /* PCIe core controller registers */
126 /* PCIe Retries & Timeout definitions */
135 * struct pcie_advk - Advk PCIe controller state
138 * @first_busno: This driver supports multiple PCIe controllers.
139 * first_busno stores the bus number of the PCIe root-port
140 * number which may vary depending on the PCIe setup
142 * @device: The pointer to PCI uclass device.
[all …]
H A Dpcie_dw_mvebu.c1 // SPDX-License-Identifier: GPL-2.0+
8 * - drivers/pci/pcie_imx.c
9 * - drivers/pci/pci_mvebu.c
10 * - drivers/pci/pcie_xilinx.c
17 #include <asm-generic/gpio.h>
97 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
103 * @first_busno: This driver supports multiple PCIe controllers.
104 * first_busno stores the bus number of the PCIe root-port
105 * number which may vary depending on the PCIe setup
132 * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
[all …]
H A Dpcie_ecam_generic.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic PCIE host provided by e.g. QEMU
17 * struct generic_ecam_pcie - generic_ecam PCIe controller state
25 * pci_generic_ecam_conf_address() - Calculate the address of a config access
27 * @bdf: Identifies the PCIe device to access
28 * @offset: The offset into the device's configuration space
31 * Calculates the address that should be accessed to perform a PCIe
32 * configuration space access for a given device identified by the PCIe
33 * controller device @pcie and the bus, device & function numbers in @bdf. If
34 * access to the device is not valid then the function will return an error
[all …]
H A DKconfig16 orgnising devices in U-Boot. For PCI, driver model keeps track of
18 device configuration support.
30 bool "Enable Aardvark PCIe driver"
35 Say Y here if you want to enable PCIe controller support on
36 Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
47 bool "Enable Aspeed PCIe driver"
51 Say Y here if you want to enable PCIe controller support on
55 bool "Generic ECAM-based PCI host controller support"
59 Say Y here if you want to enable support for generic ECAM-based
60 PCIe host controllers, such as the one emulated by QEMU.
[all …]
/openbmc/qemu/docs/
H A Dpcie_pci_bridge.txt6 PCIE-to-PCI bridge is a new method for legacy PCI
9 Previously Intel DMI-to-PCI bridge was used for this purpose.
10 But due to its strict limitations - no support of hot-plug,
11 no cross-platform and cross-architecture support - a new generic
12 PCIE-to-PCI bridge should now be used for any legacy PCI device usage
15 This generic PCIE-PCI bridge is a cross-platform device,
16 can be hot-plugged into appropriate root port (requires additional actions,
17 see 'PCIE-PCI bridge hot-plug' section),
18 and supports devices hot-plug into the bridge itself
21 Hot-plug of legacy PCI devices into the bridge
[all …]
H A Dpcie.txt6 The doc proposes best practices on how to use PCI Express (PCIe) / PCI
10 Note that the PCIe features are available only when using the 'q35'
12 Other machine types do not use PCIe at this time.
23 2. Device placement strategy
25 QEMU does not have a clear socket-device matching mechanism
26 and allows any PCI/PCI Express device to be plugged into any
28 Plugging a PCI device into a PCI Express slot might not always work and
30 Plugging a PCI Express device into a PCI slot will hide the Extended
37 2.1 Root Bus (pcie.0)
43 Note: Integrated Endpoints are not hot-pluggable.
[all …]
H A Dbypass-iommu.txt10 passthrough devices with no-iommu mode and devices go through vIOMMU in
31 qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
33 qemu -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true
35 qemu -machine q35,default_bus_bypass_iommu=true
40 qemu-system-aarch64 \
41 -machine virt,kernel_irqchip=on,iommu=smmuv3,default_bus_bypass_iommu=true \
42 -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3.0x1 \
43 -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x3.0x2,bypass_iommu=true \
46 - a default host bridge which bypass SMMUv3
47 - a pxb host bridge which go through SMMUv3
[all …]
/openbmc/qemu/docs/config/
H A Dq35-virtio-graphical.cfg1 # q35 - VirtIO guest (graphical console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-virtio-graphical.cfg
17 # ---------------------------------------------------------
19 # Using -nodefaults is required to have full control over
37 # 00:1b.0 Audio device
74 [device "pcie.1"]
75 driver = "pcie-root-port"
76 bus = "pcie.0"
[all …]
H A Dq35-virtio-serial.cfg1 # q35 - VirtIO guest (serial console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-virtio-serial.cfg \
9 # -display none -serial mon:stdio
18 # ---------------------------------------------------------
20 # Using -nodefaults is required to have full control over
43 # We use '-display none' to prevent QEMU from creating a
45 # this specific configuration, and '-serial mon:stdio' to
79 [device "pcie.1"]
[all …]
H A Dmach-virt-graphical.cfg1 # mach-virt - VirtIO guest (graphical console)
6 # $ qemu-system-aarch64 \
7 # -nodefaults \
8 # -readconfig mach-virt-graphical.cfg \
9 # -cpu host
18 # ---------------------------------------------------------
20 # Using -nodefaults is required to have full control over
59 gic-version = "host"
71 # There are two parts to the firmware: a read-only image
87 # edk2-aarch64 (pkg)
[all …]
H A Dmach-virt-serial.cfg1 # mach-virt - VirtIO guest (serial console)
6 # $ qemu-system-aarch64 \
7 # -nodefaults \
8 # -readconfig mach-virt-serial.cfg \
9 # -display none -serial mon:stdio \
10 # -cpu host
19 # ---------------------------------------------------------
21 # Using -nodefaults is required to have full control over
40 # We use '-display none' to prevent QEMU from creating a
42 # this specific configuration, and '-serial mon:stdio' to
[all …]
H A Dq35-emulated.cfg1 # q35 - Emulated guest (graphical console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-emulated.cfg
17 # ---------------------------------------------------------
19 # Using -nodefaults is required to have full control over
40 # 00:1b.0 Audio device
79 [device "ich9-pcie-port-1"]
82 bus = "pcie.0"
87 [device "ich9-pcie-port-2"]
[all …]
/openbmc/qemu/docs/specs/
H A Dpci-ids.rst5 Red Hat, Inc. donates a part of its device ID range to QEMU, to be used for
8 Contact Gerd Hoffmann <kraxel@redhat.com> to get a device ID assigned
12 --------------
14 The 1000 -> 10ff device ID range is used as follows for virtio-pci devices.
15 Note that this allocation is separate from the virtio device IDs, which are
19 network device (legacy)
21 block device (legacy)
23 balloon device (legacy)
25 console device (legacy)
27 SCSI host bus adapter device (legacy)
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DPCIeDevice_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: PCIeDevice v1.20.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2025 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
H A DPCIeFunction_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: PCIeFunction v1.6.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2025 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/installed/
H A DPCIeDevice_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!-
[all...]
H A DPCIeFunction_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: PCIeFunction v1.6.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2025 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
/openbmc/qemu/docs/system/ppc/
H A Dpowernv.rst4 PowerNV (as Non-Virtualized) is the "bare metal" platform using the
16 -----------------
23 * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
24 * Simple OCC is an on-chip micro-controller used for power management tasks.
25 * iBT device to handle BMC communication, with the internal BMC simulator
30 ---------------
36 * EEH support for PCIe Host bridge controllers.
44 --------
49 GitHub <https://github.com/open-power>`_.
52 `OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
[all …]
/openbmc/docs/designs/
H A Dredfish-spdm-attestation.md14 [TPM](https://trustedcomputinggroup.org/resource/trusted-platform-module-tpm-summary/)
15 to authenticate device identity, hardware configuration and firmware integrity.
17 unified interface for device security attestation in data centers, and provide a
18 generic implementation for the SPDM D-Bus Daemon.
27 [libspdm](https://github.com/DMTF/libspdm) provides an open-source
30 adds support for doing SPDM-based device attestation over Redfish API.
40 - New D-Bus interfaces for Redfish resources `ComponentIntegrity` and
42 - BMCWeb changes for supporting the above Redfish resources.
43 - Design for SPDM Attestation D-Bus Daemon, demonstrating how to fetch the
44 attestation results over D-Bus.
[all …]
/openbmc/libcper/specification/json/sections/
H A Dcper-pcie.json2 "$schema": "https://json-schema.org/draft/2020-12/schema",
10 … "description": "PCIe Device/Port Type as defined in the PCI Express capabilities register.",
11 "$ref": "./common/cper-json-nvp.json"
15 "description": "PCIe Spec. version supported by the platform",
44 …"description": "PCIe Root Port PCI/bridge PCI compatible device number and bus number information …
92 "description": "PCIe Device Serial Number"
110 "$ref": "./sections/cper-pcie-capabilityStructure.json"
113 "$ref": "./sections/cper-pcie-aerInfo.json"

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