| /openbmc/u-boot/include/ |
| H A D | remoteproc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Texas Instruments Incorporated - http://www.ti.com/
16 #include <dm/platdata.h> /* For platform data support - non dt world */
19 * enum rproc_mem_type - What type of memory model does the rproc use
20 * @RPROC_INTERNAL_MEMORY_MAPPED: Remote processor uses own memory and is memory
21 * mapped to the host processor over an address range.
32 * struct dm_rproc_uclass_pdata - platform data for a CPU
33 * @name: Platform-specific way of naming the Remote proc
48 * struct dm_rproc_ops - Operations that are provided by remote proc driver
50 * Return 0 on success, -ve error on fail
[all …]
|
| H A D | smem.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * The shared memory system is an allocate-only heap structure that
7 * Allocation can be done globally for all processors or to an individual processor.
22 * alloc() - allocate space for a smem item
24 * @host: remote processor id, or -1 for all processors.
27 * @return 0 if OK, -ve on error
33 * get() - Resolve ptr of size of a smem item
35 * @host: the remote processor, of -1 for all processors.
38 * @return pointer on success, NULL on error
44 * get_free_space() - Get free space in smem in bytes
[all …]
|
| /openbmc/qemu/docs/system/ |
| H A D | cpu-models-mips.rst.inc | 1 Supported CPU model configurations on MIPS hosts
9 The following CPU models are supported for use on MIPS32 hosts.
16 ``mips32r6-generic``
17 MIPS32 Processor (Release 6, 2015)
20 MIPS32 Processor (P5600, 2014)
23 MIPS32 Processor (M14K, 2009)
26 MIPS32 Processor (74K, 2007)
29 MIPS32 Processor (34K, 2006)
32 MIPS32 Processor (24K, 2003)
35 MIPS32 Processor (4K, 1999)
[all …]
|
| H A D | cpu-models-x86.rst.inc | 1 Recommendations for KVM CPU model configuration on x86 hosts
5 CPU models on x86 hosts. The goals are to maximise performance, while
51 lists the long term stable CPU model versions (eg Haswell-v4).
54 depending on the machine type is in use.
56 .. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/
58 .. csv-table:: x86-64 ABI compatibility levels
59 :file: cpu-models-x86-abi.csv
61 :header-rows: 1
67 The following CPU models are preferred for use on Intel hosts.
75 Intel Xeon Processor (ClearwaterForest, 2025)
[all …]
|
| /openbmc/u-boot/drivers/remoteproc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
4 # Texas Instruments Incorporated - http://www.ti.com/
7 menu "Remote Processor drivers"
10 # All users should depend on DM
13 depends on DM
19 depends on DM
20 depends on ARCH_K3
21 depends on OF_CONTROL
28 depends on DM
29 depends on ARCH_K3
[all …]
|
| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/ |
| H A D | Cpu.interface.yaml | 4 - name: Socket
7 Processor Socket designation on MotherBoard.
9 - name: Family
12 A free form string indicates processor family type. For example,
13 values can be "Intel Xeon processor", "AS400 Family", etc.
15 - name: EffectiveFamily
19 this processor in unsigned integer. Default set to 0x02 which is
20 defined as "Unknown" Processor Family in DSP0134 section 7.5.2.
22 - name: EffectiveModel
26 this processor in unsigned integer.
[all …]
|
| /openbmc/openpower-proc-control/extensions/phal/ |
| H A D | pdbg_utils.hpp | 18 * @param[in] procTarget - Processor target to perform the operation on
19 * @param[in] reg - The register address to read
20 * @param[out] val - The value read from the register
22 * @return 0 on success, non-0 on failure
30 * @param[in] procTarget - Processor target to perform the operation on
31 * @param[in] reg - The register address to write
32 * @param[out] val - The value to write to the register
34 * @return 0 on success, non-0 on failure
42 * @param[in] procTarget - Processor target to find the FSI target on
44 * @return Valid pointer to FSI target on success, nullptr on failure
[all …]
|
| /openbmc/u-boot/doc/driver-model/ |
| H A D | remoteproc-framework.txt | 1 # SPDX-License-Identifier: GPL-2.0+
4 # Texas Instruments Incorporated - http://www.ti.com/
7 Remote Processor Framework
11 2. How does it work - The driver
18 This is an introduction to driver-model for Remote Processors found
19 on various System on Chip(SoCs). The term remote processor is used to
20 indicate that this is not the processor on which U-Boot is operating
21 on, instead is yet another processing entity that may be controlled by
22 the processor on which we are functional.
24 The simplified model depends on a single UCLASS - UCLASS_REMOTEPROC
[all …]
|
| /openbmc/u-boot/board/intel/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
32 is built on the Chief River platform with Intel Ivybridge Processor
40 the Intel Atom Processor E6xx populated on the COM Express module
49 Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB
50 eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
56 Arduino-certified development and prototyping boards based on Intel
[all …]
|
| /openbmc/docs/designs/ |
| H A D | power-systems-memory-preserving-reboot.md | 1 # Memory preserving reboot and System Dump extraction flow on POWER Systems
9 On POWER based servers, a hypervisor firmware manages and allocates resources to
10 the logical partitions running on the server. If this hypervisor encounters an
14 required for debugging the fault. Some hypervisors on the POWER based systems
15 don't have access to a non-volatile storage to store this content after a
16 failure. A warm reboot with preserving the main memory is needed on the POWER
18 explains the high-level flow of warm reboot and extraction of the resulting dump
23 - **Boot**: The process of initializing hardware components in a computer system
26 - **Hostboot**: The firmware runs on the host processors and performs all
27 processor, bus, and memory initialization on POWER based servers.
[all …]
|
| H A D | guard-on-bmc.md | 1 # Guard on BMC
5 On systems with multiple processor units and other redundant vital resources,
9 actions required to isolate the parts will be dependant on the architecture and
32 multiple locations based on the ownership of the component. How to store the
34 the examples are guard on motherboard components managed by the host, guard on
35 the fans can be managed by the fan control application, or the guard on the
38 These records will be created when an error is encountered on an element that
39 can be isolated. The decision to create a record is based on the type of error,
45 hardware resources in a server system. The BMC creates guard records on a
47 brings the host down or on the components like a power supply or fan which can
[all …]
|
| /openbmc/ipmitool/contrib/ |
| H A D | exchange-bmc-os-info.sysconf | 1 # exchange-bmc-os-info
4 # the OS and Service Processor/Baseboard Management Controller (BMC)
9 ### Set OS Info in BMC/Service Processor ###
11 # Description: Set OS Name, Version and Hostname in the Service Processor (BMC)
15 ### Reset OS Info in BMC/Service Processor ###
17 # Description: Reset OS Name, Version and Hostname in the Service Processor (BMC).
18 # Useful when the OS Name/Hostname should be empty on reboot
22 ### Set BMC/Service Processor Info in OS ###
24 # Description: Set IP Address and URL of Service Processor/BMC in /run/bmc-info
|
| H A D | bmc-snmp-proxy.sysconf | 1 # bmc-snmp-proxy
4 # the OS and Service Processor/Baseboard Management Controller (BMC)
6 # bmc-snnmp-proxy helps redirect certain SNMP requests (to this host)
7 # destined to the Service Processor. We will need the Service Processor's
8 # SNMP community string and the OID of the Service Processor's SNMP agent.
10 # For redirecting Traps from the Service Processor to the trap sink
17 ### Configure SNMP proxy to BMC/Service Processor ###
19 ### Service Processor/BMC SNMP Community String.
21 # Description: Set community string of the Service Processor (BMC)'s
27 ### OEM Specific OID of Service Processor
[all …]
|
| /openbmc/qemu/docs/system/riscv/ |
| H A D | microblaze-v-generic.rst | 1 Microblaze-V generic board (``amd-microblaze-v-generic``)
3 The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
4 adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
5 64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
6 compatible with the classic MicroBlaze™ V processor (i.e it is a drop in
7 replacement for the classic MicroBlaze™ processor in existing RTL designs).
10 https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture
14 - timer
15 - uartlite
16 - uart16550
[all …]
|
| /openbmc/u-boot/doc/ |
| H A D | README.xtensa | 1 U-Boot for the Xtensa Architecture
5 -------------------------------------
7 Xtensa is a configurable processor architecture from Tensilica, Inc.
8 Diamond Cores are pre-configured instances available for license and
12 and custom instructions, registers and co-processors. The custom core
14 Processor Generator.
18 Xtensa CPUs in U-Boot. Therefore, there is only a single 'xtensa' CPU
19 in the cpu tree of U-Boot.
21 In the same manner as the Linux port to Xtensa, U-Boot adapts to an
24 abstraction layer (HAL). For the purpose of U-Boot, the HAL consists only
[all …]
|
| /openbmc/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 2 --------
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
|
| /openbmc/libcper/specification/document/ |
| H A D | cper-json-specification.tex | 7 \title{CPER-JSON Specification}
47 in a human-readable JSON format, intended to be interoperable with standard CPER binary.
50 …ive JSON schema\footnote{As defined by \href{https://json-schema.org/draft/2020-12/json-schema-cor…
104 …xtbf{optional}) & If validation bit is set, GUID identifying the partition on which the error occu…
110 …bined with the \texttt{creatorID} field, uniquely identifies this error record on a given system.\\
152 This structure describes the enabled flag on a given CPER record header.
172 validationBits.fruIDValid & boolean & Whether the "fruID" field on this section descriptor contains…
173 validationBits.fruStringValid & boolean & Whether the "fruString" field on this section descriptor …
178 …ypes of sectoin body are defined in UEFI specification section N.2.2 Table N-5 and section N.2.4.\\
191 This structure describes the enabled flags on a given CPER section descriptor.
[all …]
|
| /openbmc/openpower-occ-control/ |
| H A D | README.md | 3 This service will handle communications to the On-Chip Controller (OCC) on Power
4 processors. The OCC provides processor and memory temperatures, power readings,
15 builddir && ninja -C builddir.
19 The server will start automatically after BMC is powered on.
33 IBM EnergyScale for Power10 Processor-Based Systems whitepaper:
37 <https://github.com/open-power/docs/blob/P10/occ/OCC_P10_FW_Interfaces_v1_17.pdf>
39 OCC Firmware: <https://github.com/open-power/occ/tree/master-p10>
43 IBM EnergyScale for POWER9 Processor-Based Systems:
44 <https://www-01.ibm.com/common/ssi/cgi-bin/ssialias?htmlfid=49019149USEN&>
47 <https://github.com/open-power/docs/blob/P9/occ/OCC_P9_FW_Interfaces.pdf>
|
| /openbmc/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
|
| /openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/ |
| H A D | 0001-remoteproc-Add-Arm-remoteproc-driver.patch | 10 switch on or off the remote processor.
12 The current use case is Corstone-1000 External System (Cortex-M3).
20 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
21 Upstream-Status: Denied [Agreement reached: https://lore.kernel.org/all/20241009094635.GA14639@e130…
22 ---
30 diff --git a/MAINTAINERS b/MAINTAINERS
32 --- a/MAINTAINERS
34 @@ -1764,6 +1764,12 @@ S: Maintained
35 F: Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml
36 F: drivers/irqchip/irq-vic.c
[all …]
|
| /openbmc/phosphor-dbus-interfaces/yaml/com/ibm/Dump/Entry/ |
| H A D | SBE.interface.yaml | 4 Self Boot Engine(SBE) is a microcontroller that sits inside the processor to
6 accessing certain control functions on the processor. During the booting or
12 There will be one instance of SBE on each processor. Implement this
16 - name: ErrorLogId
21 The value should be a 32-bit unsigned integer.
23 - name: FailingUnitId
28 value should be a 32-bit unsigned integer.
|
| /openbmc/u-boot/drivers/firmware/ |
| H A D | ti_sci.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
9 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
10 * Based on drivers/firmware/ti_sci.h from Linux.
44 /* Processor Control Messages */
54 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
75 * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
86 * struct ti_sci_msg_resp_version - Response for a message
108 * struct ti_sci_msg_req_reboot - Reboot the SoC
119 * struct ti_sci_msg_board_config - Board configuration message
137 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
[all …]
|
| /openbmc/u-boot/include/linux/soc/ti/ |
| H A D | ti_sci_protocol.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Based on include/linux/soc/ti/ti_sci_protocol.h from Linux.
6 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
15 * struct ti_sci_version_info - version information structure
33 * struct ti_sci_board_ops - Board config operations
61 * struct ti_sci_dev_ops - Device control operations
73 * @get_context_loss_count: Command to retrieve context loss counter - this
76 * - count: pointer to u32 which will retrieve counter
80 * - req_state: Returns requested idle state
85 * - req_state: Returns requested stop state
[all …]
|
| /openbmc/dbus-sensors/include/linux/ |
| H A D | peci-ioctl.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2019 Intel Corporation */
4 // clang-format off
48 * enum peci_cmd - PECI client commands
59 * maintained in downstream devices external to the processor
61 * maintained in downstream devices external to the processor
63 * space that resides within the processor
65 * space that resides within the processor
67 * Available commands depend on client's PECI revision.
91 * struct peci_xfer_msg - raw PECI transfer command
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | imx-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
275 u32 cpxtype; /* Processor x Type Register */
276 u32 cpxnum; /* Processor x Number Register */
277 u32 cpxmaster; /* Processor x Master Number Register */
278 u32 cpxcount; /* Processor x Count Register */
279 u32 cpxcfg0; /* Processor x Configuration 0 Register */
280 u32 cpxcfg1; /* Processor x Configuration 1 Register */
281 u32 cpxcfg2; /* Processor x Configuration 2 Register */
282 u32 cpxcfg3; /* Processor x Configuration 3 Register */
[all …]
|