| /openbmc/linux/arch/sh/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
78 The SuperH is a RISC processor targeted for use in embedded systems
81 <http://www.linux-sh.org/>.
85 depends on BUG
95 depends on SMP && PREEMPTION
127 depends on !SH_SH4202_MICRODEV && !SH_SHMIN && !SH_HP6XX && \
152 # Processor families
209 depends on CPU_SH4 || CPU_SH4A
214 prompt "Processor sub-type selection"
217 # Processor subtypes
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| /openbmc/linux/arch/m68k/ |
| H A D | Kconfig.cpu | 1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
10 the full 68000 processor instruction set.
12 of the 68000 processor family. They are mainly targeted at embedded
13 applications, and are all System-On-Chip (SOC) devices, as opposed
15 processor instruction set.
16 If you anticipate running this kernel on a computer with a classic
17 MC68xxx processor, select M68KCLASSIC.
18 If you anticipate running this kernel on a computer with a ColdFire
19 processor, select COLDFIRE.
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
[all …]
|
| H A D | frontend.json | 47 "BriefDescription": "Number of I-ERAT reloads",
59 "BriefDescription": "IERAT Miss (Not implemented as DI on POWER6)",
89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
[all …]
|
| H A D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
125 …"BriefDescription": "Conditional Branch Completed on BR0 (1st branch in group) in which the HW pre…
131 …"BriefDescription": "Conditional Branch Completed on BR1 (2nd branch in group) in which the HW pre…
143 …"BriefDescription": "Conditional Branch Completed on BR0 that used the Count Cache for Target Pred…
149 …"BriefDescription": "Conditional Branch Completed on BR1 that used the Count Cache for Target Pred…
161 …on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-for…
167 …on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-for…
179 …"BriefDescription": "Conditional Branch Completed on BR0 that used the Link Stack for Target Predi…
[all …]
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| /openbmc/linux/drivers/remoteproc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
5 bool "Support for Remote Processor subsystem"
6 depends on HAS_DMA
13 are mainly used on embedded systems.
28 depends on ARCH_MXC
29 depends on HAVE_ARM_SMCCC
33 processor framework.
39 depends on ARCH_MXC
40 depends on HAVE_ARM_SMCCC
44 processor framework.
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| /openbmc/u-boot/include/ |
| H A D | remoteproc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Texas Instruments Incorporated - http://www.ti.com/
16 #include <dm/platdata.h> /* For platform data support - non dt world */
19 * enum rproc_mem_type - What type of memory model does the rproc use
20 * @RPROC_INTERNAL_MEMORY_MAPPED: Remote processor uses own memory and is memory
21 * mapped to the host processor over an address range.
32 * struct dm_rproc_uclass_pdata - platform data for a CPU
33 * @name: Platform-specific way of naming the Remote proc
48 * struct dm_rproc_ops - Operations that are provided by remote proc driver
50 * Return 0 on success, -ve error on fail
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| /openbmc/qemu/docs/system/ |
| H A D | cpu-models-mips.rst.inc | 1 Supported CPU model configurations on MIPS hosts
9 The following CPU models are supported for use on MIPS32 hosts.
16 ``mips32r6-generic``
17 MIPS32 Processor (Release 6, 2015)
20 MIPS32 Processor (P5600, 2014)
23 MIPS32 Processor (M14K, 2009)
26 MIPS32 Processor (74K, 2007)
29 MIPS32 Processor (34K, 2006)
32 MIPS32 Processor (24K, 2003)
35 MIPS32 Processor (4K, 1999)
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|
| /openbmc/linux/Documentation/staging/ |
| H A D | rpmsg.rst | 2 Remote Processor Messaging (rpmsg) Framework
14 Modern SoCs typically employ heterogeneous remote processor devices in
17 flavor of real-time OS.
19 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
20 Typically, the dual cortex-A9 is running Linux in a SMP configuration,
25 hardware accelerators, and therefore are often used to offload CPU-intensive
26 multimedia tasks from the main application processor.
28 These remote processors could also be used to control latency-sensitive
34 hardware accessible only by the remote processor, reserving kernel-controlled
35 resources on behalf of the remote processor, etc..).
[all …]
|
| H A D | remoteproc.rst | 2 Remote Processor Framework
8 Modern SoCs typically have heterogeneous remote processor devices in asymmetric
10 of operating system, whether it's Linux or any other flavor of real-time OS.
12 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
13 In a typical configuration, the dual cortex-A9 is running Linux in a SMP
18 control (power on, load firmware, power off) those remote processors while
22 platform-specific remoteproc drivers only need to provide a few low-level
24 (for more information about the virtio-based rpmsg bus and its drivers,
29 existing virtio drivers with remote processor backends at a minimal development
39 Boot a remote processor (i.e. load its firmware, power it on, ...).
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| /openbmc/linux/arch/arm/mm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
4 # Select CPU types depending on the architecture selected. This selects
11 depends on !MMU
17 A 32-bit RISC microprocessor based on the ARM7 processor core
20 Say Y if you want support for the ARM7TDMI processor.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
39 Say Y if you want support for the ARM720T processor.
45 depends on !MMU
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
[all …]
|
| /openbmc/linux/arch/arm/mach-imx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 depends on ((ARCH_MULTI_V4T || ARCH_MULTI_V5) && CPU_LITTLE_ENDIAN) || \
14 Support for Freescale MXC/iMX-based family of processors
47 This enables support for Freescale i.MX31 processor
54 This enables support for Freescale i.MX35 processor
66 This enables support for Freescale i.MX1 processor
78 This enables support for Freescale i.MX25 processor
86 This enables support for Freescale i.MX27 processor
92 comment "Cortex-A platforms"
105 This enables support for Freescale i.MX50 processor.
[all …]
|
| /openbmc/linux/tools/power/cpupower/man/ |
| H A D | cpupower-monitor.1 | 1 .TH CPUPOWER\-MONITOR "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-monitor \- Report processor frequency and idle statistics
7 .RB "\-l"
10 .RB [ -c ] [ "\-m <mon1>," [ "<mon2>,..." ] ]
11 .RB [ "\-i seconds" ]
14 .RB [ -c ][ "\-m <mon1>," [ "<mon2>,..." ] ]
18 \fBcpupower-monitor \fP reports processor topology, frequency and idle power
22 \fBcpupower-monitor \fP implements independent processor sleep state and
24 directly reading out hardware registers. Use \-l to get an overview which are
25 supported on your system.
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
|
| /openbmc/linux/drivers/media/platform/renesas/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
9 depends on V4L_PLATFORM_DRIVERS
10 depends on VIDEO_DEV
11 depends on ARCH_SHMOBILE || ARCH_R7S72100 || COMPILE_TEST
18 tristate "R-Car Image Signal Processor (ISP)"
19 depends on V4L_PLATFORM_DRIVERS
20 depends on VIDEO_DEV && OF
21 depends on ARCH_RENESAS || COMPILE_TEST
27 Support for Renesas R-Car Image Signal Processor (ISP).
28 Enable this to support the Renesas R-Car Image Signal
[all …]
|
| /openbmc/linux/Documentation/admin-guide/pm/ |
| H A D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
47 Each ``MWAIT`` hint value is interpreted by the processor as a license to
[all …]
|
| H A D | intel_pstate.rst | 1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
62 depends on what kernel command line options are used and on the capabilities of
63 the processor.
[all …]
|
| /openbmc/openbmc-test-automation/lib/ras/ |
| H A D | host_utils.robot | 15 Getscom Operations On OS
16 [Documentation] Executes getscom command on OS with the given
20 # input_cmd -l|--list-chips
21 # -c|--chip <chip-id> <addr>
26 Gard Operations On OS
27 [Documentation] Executes opal-gard command on OS with the given
33 ${output} ${stderr} ${rc}= OS Execute Command opal-gard ${input_cmd}
36 Putscom Operations On OS
37 [Documentation] Executes putscom command on OS with the given
41 # proc_chip_id Processor ID (e.g '0', '8').
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|
| /openbmc/linux/Documentation/powerpc/ |
| H A D | elf_hwcaps.rst | 11 ---------------
13 Some hardware or software features are only available on some CPU
32 Where software relies on a feature described by a HWCAP, it should check the
46 -------------
50 whether this class is available to be used, but the specifics depend on the
56 -------------
60 mutually exclusive, the exact meaning of the HWCAP flag may depend on
65 -------------------
67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
71 ---------------------------------
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| /openbmc/linux/Documentation/core-api/ |
| H A D | this_cpu_ops.rst | 9 variables associated with the *currently* executing processor. This is
12 specific processor).
14 this_cpu operations add a per cpu variable offset to the processor
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
21 processor is not changed between the calculation of the address and
22 the operation on the data.
24 Read-modify-write operations are of particular interest. Frequently
33 data specific to the currently executing processor. Only the current
34 processor should be accessing that variable and therefore there are no
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | asc7621.rst | 20 Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as
21 Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has
23 Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in
28 have used registers below 20h for vendor-specific functions in addition
29 to those in the Intel-specified vendor range.
32 The fan speed control uses this finer value to produce a "step-less" fan
33 PWM output. These two bytes are "read-locked" to guarantee that once a
34 high or low byte is read, the other byte is locked-in until after the
37 sheet says 10-bits of resolution, although you may find the lower bits
47 We offer GPIO features on the former VID pins. These are open-drain
[all …]
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/ |
| H A D | Cpu.interface.yaml | 4 - name: Socket
7 Processor Socket designation on MotherBoard.
9 - name: Family
12 A free form string indicates processor family type. For example,
13 values can be "Intel Xeon processor", "AS400 Family", etc.
15 - name: EffectiveFamily
19 this processor in unsigned integer. Default set to 0x02 which is
20 defined as "Unknown" Processor Family in DSP0134 section 7.5.2.
22 - name: EffectiveModel
26 this processor in unsigned integer.
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 7 …processor to begin executing instructions long before the branch true execution path is known. All…
15 …processor to begin executing instructions long before the branch true execution path is known. All…
24 …processor to begin executing instructions long before the branch true execution path is known. All…
33 …processor to begin executing instructions long before the branch true execution path is known. All…
42 …processor to begin executing instructions long before the branch true execution path is known. All…
51 …processor to begin executing instructions long before the branch true execution path is known. All…
60 …processor to begin executing instructions long before the branch true execution path is known. All…
69 …processor to begin executing instructions long before the branch true execution path is known. All…
78 …processor to begin executing instructions long before the branch true execution path is known. All…
87 …processor to begin executing instructions long before the branch true execution path is known. All…
[all …]
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| /openbmc/linux/Documentation/admin-guide/hw-vuln/ |
| H A D | processor_mmio_stale_data.rst | 2 Processor MMIO Stale Data Vulnerabilities
5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
15 changes, depending on the platform and usage model. Some of these mitigations
22 one microarchitectural buffer or register to another. Processor MMIO Stale Data
24 read into an architectural, software-visible state or sampled from a buffer or
28 -----------------------------------------
29 Stale data may propagate from fill buffers (FB) into the non-coherent portion
30 of the uncore on some non-coherent writes. Fill buffer propagation by itself
35 -------------------------------------
38 shared by all client cores. For non-coherent reads that go to sideband
[all …]
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| /openbmc/linux/Documentation/driver-api/pm/ |
| H A D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 fetch and execute instructions: hardware threads, if present, or processor
19 there are no tasks to run on it except for the special "idle" task associated
20 with it, there is an opportunity to save energy for the processor that it
22 instructions from memory and putting some of the processor's functional units
23 depended on by it into an idle state in which they will draw less power.
27 (from the kernel perspective) and ask the processor to use (or "enter") that
31 The design of ``CPUIdle`` is modular and based on the code duplication avoidance
32 principle, so the generic code that in principle need not depend on the hardware
35 units: *governors* responsible for selecting idle states to ask the processor
[all …]
|