Lines Matching +full:on +full:- +full:processor
1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
4 # Select CPU types depending on the architecture selected. This selects
11 depends on !MMU
17 A 32-bit RISC microprocessor based on the ARM7 processor core
20 Say Y if you want support for the ARM7TDMI processor.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
39 Say Y if you want support for the ARM720T processor.
45 depends on !MMU
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
57 Say Y if you want support for the ARM740T processor.
63 depends on !MMU
69 A 32-bit RISC microprocessor based on the ARM9 processor core
72 Say Y if you want support for the ARM9TDMI processor.
91 Say Y if you want support for the ARM920T processor.
111 Say Y if you want support for the ARM922T processor.
131 Say Y if you want support for the ARM925T processor.
148 there is no documentation on it at the ARM corporate website.
150 Say Y if you want support for the ARM926T processor.
165 The FA526 is a version of the ARMv4 compatible processor with
168 Say Y if you want support for the FA526 processor.
174 depends on !MMU
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
187 Say Y if you want support for the ARM940T processor.
190 # ARM946E-S
193 depends on !MMU
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
205 Say Y if you want support for the ARM946E-S processor.
208 # ARM1020 - needs validating
221 The ARM1020 is the 32K cached version of the ARM10 processor,
222 with an addition of a floating-point unit.
224 Say Y if you want support for the ARM1020 processor.
227 # ARM1020E - needs validating
230 depends on n
255 embedded trace macrocell, and a floating-point unit.
257 Say Y if you want support for the ARM1022E processor.
260 # ARM1026EJ-S
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
275 Say Y if you want support for the ARM1026EJ-S processor.
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
296 Say Y if you want support for the SA-110 processor.
359 depends on CPU_FEROCEON && !CPU_ARM926T
364 Relevant for Feroceon-1850 and early Feroceon-2850.
437 depends on !MMU
446 # Figure out what processor architecture version we should be using.
447 # This defines the compiler instruction set which depends on the machine type.
554 # The copy-page model
590 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
616 Processor has the CP15 register.
622 Processor has the CP15 register, which has MMU related registers.
628 Processor has the CP15 register, which has MPU related registers.
637 and to handle IO-space as a special type of memory by assigning
642 depends on CPU_V7M
651 interrupts supported by the NVIC on Cortex-M family.
656 # CPU supports 36-bit I/O
661 comment "Processor Features"
665 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
670 Say Y if you have an ARMv7 processor supporting the LPAE page
672 4GB limit. The resulting kernel image will not run on
679 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
683 depends on CPU_THUMB_CAPABLE && !CPU_32v4
701 depends on CPU_V7
704 make use of it. Say N for code that can run on CPUs without ThumbEE.
711 Extensions to install hypervisors without run-time firmware
720 depends on CPU_V7
738 on an external transaction monitoring block called a global
750 bool "Built little-endian kernel"
752 Say Y if you plan on running a kernel in little-endian mode.
757 bool "Build big-endian kernel"
758 depends on !LD_IS_LLD
760 Say Y if you plan on running a kernel in big-endian mode.
761 This works on many machines using ARMv6 or newer processors
762 but requires big-endian user space.
764 The only ARMv5 platform with big-endian support is
771 depends on CPU_BIG_ENDIAN
774 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
778 depends on CPU_BIG_ENDIAN
781 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
784 depends on !MMU && CPU_CP15 && !CPU_ARM740T
788 The exception vector can vary depending on the platform
795 bool "Disable I-Cache (I-bit)"
796 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
798 Say Y here to disable the processor instruction cache. Unless
802 bool "Workaround for I-Cache line size mismatch between CPU cores"
803 depends on SMP && CPU_V7
805 Some big.LITTLE systems have I-Cache line size mismatch between
807 proper I-Cache support on such systems. If unsure, say N.
810 bool "Disable D-Cache (C-bit)"
811 depends on (CPU_CP15 && !SMP) || CPU_V7M
813 Say Y here to disable the processor data cache. Unless
818 depends on CPU_ARM740T || CPU_ARM946E
820 default 0x00002000 # default size for ARM946E-S
823 ARM946E-S case, it can vary from 0KB to 1MB.
830 bool "Force write through D-cache"
831 …depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T…
839 …depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISA…
841 Say Y here to use the predictable round-robin cache replacement
846 …depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CP…
856 depends on CPU_SPECTRE
859 Speculation attacks against some high-performance processors rely
860 on being able to manipulate the branch predictor for a victim
866 This config option will take CPU-specific actions to harden
867 the branch predictor against aliasing attacks and may rely on
875 depends on CPU_SPECTRE
878 Speculation attacks against some high-performance processors can
887 An SMP system using a pre-ARMv6 processor (there are apparently
896 depends on MMU
905 run on ARMv4 through to ARMv7 without modification.
913 If all of the binaries and libraries which run on your platform
917 relying on those helpers is run, it will receive a SIGILL signal,
925 depends on AEABI && MMU && CPU_V7
942 depends on CPU_V6K && SMP
945 The Snoop Control Unit on ARM11MPCore does not detect the
947 functions may leave stale cache entries on other CPUs. By
953 Note that the workaround is only valid on processors that do
954 not perform speculative loads into the D-cache. For such
970 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
971 depends on ARCH_BRCMSTB
974 This option enables the Broadcom Brahma-B15 read-ahead cache
975 controller. If disabled, the read-ahead cache remains off.
979 depends on ARCH_MV78XX0 || ARCH_MVEBU
987 depends on CACHE_FEROCEON_L2
1016 depends on PERF_EVENTS
1051 Under some condition the effect of cache sync operation on
1063 On revisions of the PL310 prior to r3p2, the Store Buffer does
1064 not automatically drain. This can cause normal, non-cacheable
1068 on systems with an outer cache, the store buffer is drained
1075 depends on (CPU_MOHAWK || CPU_PJ4)
1080 found on PJ1/PJ4).
1084 depends on ARCH_UNIPHIER
1093 bool "Enable the L2 cache on XScale3"
1094 depends on CPU_XSC3
1098 This option enables the L2 cache on XScale3.
1118 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1124 so on these CPUs, this option is forced on.
1127 on ARMv6 CPUs, but since they do not have aggressive speculative
1131 and therefore turning this on may result in unpredictable driver
1134 On some of the beefier ARMv7-M machines (with DMA and write
1144 bool "Make rodata strictly non-executable"
1145 depends on STRICT_KERNEL_RWX
1148 If this is set, rodata will be made explicitly non-executable. This
1149 provides protection on the rare chance that attackers might find and
1151 additional section-aligned split of rodata from kernel text so it
1152 can be made explicitly non-executable. This padding may waste memory