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/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Darm,mhu.yaml99 interrupts = <0 36 4>, /* LP-NonSecure */
100 <0 35 4>, /* HP-NonSecure */
110 mboxes = <&mhuA 1>; /* HP-NonSecure */
111 shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
131 interrupts = <0 36 4>, /* LP-NonSecure */
132 <0 35 4>, /* HP-NonSecure */
142 mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */
143 <&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */
160 mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */
161 <&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */
/openbmc/qemu/include/hw/intc/
H A Darmv7m_nvic.h47 * a Secure and a NonSecure version of the exception and its state):
50 * they may be configurable to target either Secure or NonSecure state.
91 * @secure: false for non-banked exceptions or for the nonsecure
104 * @secure: false for non-banked exceptions or for the nonsecure
117 * @secure: false for non-banked exceptions or for the nonsecure
165 * @secure: false for non-banked exceptions or for the nonsecure
H A Darm_gicv3_common.h90 * Group0, Group1 (Secure) and Group1 (NonSecure)
/openbmc/qemu/target/arm/
H A Didau.h51 * ns: true if the address is NonSecure
52 * nsc: true if the address is NonSecure-callable
H A Dptw.c33 * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
40 * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
52 * the ptw read are Secure and NonSecure, and the in_ptw_idx
169 * Secure IPA or a NonSecure IPA, which we know from whether this is
376 * R_CPDSB: A NonSecure physical address input exceeding PPS in granule_protection_check()
536 * the ptw read might be to the Secure or the NonSecure space in S2_security_space()
557 * whether the faulting IPA is in the Secure or NonSecure in fault_s1ns()
1421 /* Input NonSecure must have output NonSecure. */ in get_S1prot()
1877 * NonSecure. With RME, the EL3 translation regime does not change in get_phys_addr_lpae()
1878 * from Root to NonSecure. in get_phys_addr_lpae()
[all …]
H A Dcpu.h2775 * + NonSecure EL1 & 0 stage 1
2776 * + NonSecure EL1 & 0 stage 2
2777 * + NonSecure EL2
2778 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2788 * + NonSecure PL1 & 0 stage 1
2789 * + NonSecure PL1 & 0 stage 2
2790 * + NonSecure PL2
2821 * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure,
2837 * Stage2 NonSecure
3129 * the secure or nonsecure bank of banked registers; note that this is not
/openbmc/linux/tools/arch/arm/include/uapi/asm/
H A Dkvm.h154 * For KVM currently all guest registers are nonsecure, but we reserve a bit
155 * in the encoding to distinguish secure from nonsecure for AArch32 system
157 * register, and 0 for the nonsecure banked register or if the register is
/openbmc/qemu/linux-headers/asm-arm/
H A Dkvm.h154 * For KVM currently all guest registers are nonsecure, but we reserve a bit
155 * in the encoding to distinguish secure from nonsecure for AArch32 system
157 * register, and 0 for the nonsecure banked register or if the register is
/openbmc/qemu/include/hw/arm/
H A Dlinux-boot-if.h33 * @secure_boot: true if we are booting Secure, false for NonSecure
/openbmc/qemu/docs/system/arm/
H A Dvirt.rst29 - Either one or two PL011 UARTs for the NonSecure World
51 The second NonSecure UART only exists if a backend is configured
/openbmc/qemu/hw/misc/
H A Dtz-msc.c91 * whether bus master is configured as Secure or NonSecure in tz_msc_check()
97 /* NonSecure region -- always forward as NS transaction */ in tz_msc_check()
/openbmc/qemu/include/exec/
H A Dmemattrs.h20 * bus (such as the ARM Secure/NonSecure bit). We define them
/openbmc/qemu/include/hw/misc/
H A Dtz-msc.h35 * treated as nonsecure, or 0 for secure
H A Dtz-ppc.h51 * accessible to NonSecure transactions
/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra194-cbb.yaml59 CCPLEX receives secure or nonsecure interrupt depending on error type.
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dmisc_arria10.c64 + * The idea is to set all security policies to be normal, nonsecure
/openbmc/qemu/hw/intc/
H A Darm_gic_common.c340 /* We're directly booting a kernel into NonSecure. If this GIC in arm_gic_common_linux_init()
342 * to have all the interrupts be NonSecure (this is a job that in arm_gic_common_linux_init()
H A Darm_gicv3_common.c597 /* We're directly booting a kernel into NonSecure. If this GIC in arm_gic_common_linux_init()
599 * to have all the interrupts be NonSecure (this is a job that in arm_gic_common_linux_init()
H A Darmv7m_nvic.c497 * @secure: false for non-banked exceptions or for the nonsecure
727 * continue to do so, even if HF normally targets NonSecure. in armv7m_nvic_set_pending_lazyfp()
1040 * NonSecure and the highest priority pending and enabled in nvic_readl()
2172 * return M_REG_NS to use the nonsecure vector (including for in shpr_bank()
2185 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */ in shpr_bank()
2192 /* Not banked, RAZ/WI from nonsecure */ in shpr_bank()
2666 * n == 0 : NonSecure systick in nvic_systick_trigger()
/openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/trusted-firmware-m/
H A Dtrusted-firmware-m.inc59 PACKAGECONFIG[test-nonsecure] = "-DTEST_NS=ON,-DTEST_NS=OFF"
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Darm,scpi.yaml178 shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
/openbmc/openbmc-tools/openbmctool/
H A DREADME.md155 #### NonSecure subsubsection
/openbmc/u-boot/arch/arm/lib/
H A Dgic_64.S132 msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
/openbmc/qemu/hw/arm/
H A Darmv7m.c340 * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't in armv7m_realize()
406 * NonSecure alias SCS; secure accesses to this behave like NS accesses in armv7m_realize()
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-etm4x.h706 #define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */
707 #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */
708 #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */

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