1ff8f06eeSShlomo Pongratz /*
2ff8f06eeSShlomo Pongratz * ARM GIC support
3ff8f06eeSShlomo Pongratz *
4ff8f06eeSShlomo Pongratz * Copyright (c) 2012 Linaro Limited
5ff8f06eeSShlomo Pongratz * Copyright (c) 2015 Huawei.
607e2034dSPavel Fedin * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7ff8f06eeSShlomo Pongratz * Written by Peter Maydell
807e2034dSPavel Fedin * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
9ff8f06eeSShlomo Pongratz *
10ff8f06eeSShlomo Pongratz * This program is free software; you can redistribute it and/or modify
11ff8f06eeSShlomo Pongratz * it under the terms of the GNU General Public License as published by
12ff8f06eeSShlomo Pongratz * the Free Software Foundation, either version 2 of the License, or
13ff8f06eeSShlomo Pongratz * (at your option) any later version.
14ff8f06eeSShlomo Pongratz *
15ff8f06eeSShlomo Pongratz * This program is distributed in the hope that it will be useful,
16ff8f06eeSShlomo Pongratz * but WITHOUT ANY WARRANTY; without even the implied warranty of
17ff8f06eeSShlomo Pongratz * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18ff8f06eeSShlomo Pongratz * GNU General Public License for more details.
19ff8f06eeSShlomo Pongratz *
20ff8f06eeSShlomo Pongratz * You should have received a copy of the GNU General Public License along
21ff8f06eeSShlomo Pongratz * with this program; if not, see <http://www.gnu.org/licenses/>.
22ff8f06eeSShlomo Pongratz */
23ff8f06eeSShlomo Pongratz
24ff8f06eeSShlomo Pongratz #ifndef HW_ARM_GICV3_COMMON_H
25ff8f06eeSShlomo Pongratz #define HW_ARM_GICV3_COMMON_H
26ff8f06eeSShlomo Pongratz
27ff8f06eeSShlomo Pongratz #include "hw/sysbus.h"
28ff8f06eeSShlomo Pongratz #include "hw/intc/arm_gic_common.h"
29db1015e9SEduardo Habkost #include "qom/object.h"
30ff8f06eeSShlomo Pongratz
3107e2034dSPavel Fedin /*
3207e2034dSPavel Fedin * Maximum number of possible interrupts, determined by the GIC architecture.
3307e2034dSPavel Fedin * Note that this does not include LPIs. When implemented, these should be
3407e2034dSPavel Fedin * dealt with separately.
3507e2034dSPavel Fedin */
3607e2034dSPavel Fedin #define GICV3_MAXIRQ 1020
3707e2034dSPavel Fedin #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
3807e2034dSPavel Fedin
39c694cb4cSShashi Mallela #define GICV3_LPI_INTID_START 8192
40c694cb4cSShashi Mallela
41ae3b3ba1SPeter Maydell /*
42ae3b3ba1SPeter Maydell * The redistributor in GICv3 has two 64KB frames per CPU; in
43ae3b3ba1SPeter Maydell * GICv4 it has four 64KB frames per CPU.
44ae3b3ba1SPeter Maydell */
451e575b66SEric Auger #define GICV3_REDIST_SIZE 0x20000
46ae3b3ba1SPeter Maydell #define GICV4_REDIST_SIZE 0x40000
471e575b66SEric Auger
48c8efd802SAndrew Jones /* Number of SGI target-list bits */
49c8efd802SAndrew Jones #define GICV3_TARGETLIST_BITS 16
50c8efd802SAndrew Jones
514eb833b5SPeter Maydell /* Maximum number of list registers (architectural limit) */
524eb833b5SPeter Maydell #define GICV3_LR_MAX 16
534eb833b5SPeter Maydell
5407e2034dSPavel Fedin /* For some distributor fields we want to model the array of 32-bit
5507e2034dSPavel Fedin * register values which hold various bitmaps corresponding to enabled,
5607e2034dSPavel Fedin * pending, etc bits. These macros and functions facilitate that; the
5707e2034dSPavel Fedin * APIs are generally modelled on the generic bitmap.h functions
5807e2034dSPavel Fedin * (which are unsuitable here because they use 'unsigned long' as the
5907e2034dSPavel Fedin * underlying storage type, which is very awkward when you need to
6007e2034dSPavel Fedin * access the data as 32-bit values.)
6107e2034dSPavel Fedin * Each bitmap contains a bit for each interrupt. Although there is
6207e2034dSPavel Fedin * space for the PPIs and SGIs, those bits (the first 32) are never
6307e2034dSPavel Fedin * used as that state lives in the redistributor. The unused bits are
6407e2034dSPavel Fedin * provided purely so that interrupt X's state is always in bit X; this
6507e2034dSPavel Fedin * avoids bugs where we forget to subtract GIC_INTERNAL from an
6607e2034dSPavel Fedin * interrupt number.
6707e2034dSPavel Fedin */
683666331aSPhilippe Mathieu-Daudé #define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32)
6907e2034dSPavel Fedin
7007e2034dSPavel Fedin #define GIC_DECLARE_BITMAP(name) \
7107e2034dSPavel Fedin uint32_t name[GICV3_BMP_SIZE]
7207e2034dSPavel Fedin
7307e2034dSPavel Fedin #define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
7407e2034dSPavel Fedin #define GIC_BIT_WORD(nr) ((nr) / 32)
7507e2034dSPavel Fedin
gic_bmp_set_bit(int nr,uint32_t * addr)7607e2034dSPavel Fedin static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
7707e2034dSPavel Fedin {
7807e2034dSPavel Fedin uint32_t mask = GIC_BIT_MASK(nr);
7907e2034dSPavel Fedin uint32_t *p = addr + GIC_BIT_WORD(nr);
8007e2034dSPavel Fedin
8107e2034dSPavel Fedin *p |= mask;
8207e2034dSPavel Fedin }
8307e2034dSPavel Fedin
gic_bmp_clear_bit(int nr,uint32_t * addr)8407e2034dSPavel Fedin static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
8507e2034dSPavel Fedin {
8607e2034dSPavel Fedin uint32_t mask = GIC_BIT_MASK(nr);
8707e2034dSPavel Fedin uint32_t *p = addr + GIC_BIT_WORD(nr);
8807e2034dSPavel Fedin
8907e2034dSPavel Fedin *p &= ~mask;
9007e2034dSPavel Fedin }
9107e2034dSPavel Fedin
gic_bmp_test_bit(int nr,const uint32_t * addr)9207e2034dSPavel Fedin static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
9307e2034dSPavel Fedin {
9407e2034dSPavel Fedin return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
9507e2034dSPavel Fedin }
9607e2034dSPavel Fedin
gic_bmp_replace_bit(int nr,uint32_t * addr,int val)9707e2034dSPavel Fedin static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
9807e2034dSPavel Fedin {
9907e2034dSPavel Fedin uint32_t mask = GIC_BIT_MASK(nr);
10007e2034dSPavel Fedin uint32_t *p = addr + GIC_BIT_WORD(nr);
10107e2034dSPavel Fedin
10207e2034dSPavel Fedin *p &= ~mask;
10307e2034dSPavel Fedin *p |= (val & 1U) << (nr % 32);
10407e2034dSPavel Fedin }
10507e2034dSPavel Fedin
10607e2034dSPavel Fedin /* Return a pointer to the 32-bit word containing the specified bit. */
gic_bmp_ptr32(uint32_t * addr,int nr)10707e2034dSPavel Fedin static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
10807e2034dSPavel Fedin {
10907e2034dSPavel Fedin return addr + GIC_BIT_WORD(nr);
11007e2034dSPavel Fedin }
11107e2034dSPavel Fedin
11207e2034dSPavel Fedin typedef struct GICv3State GICv3State;
11307e2034dSPavel Fedin typedef struct GICv3CPUState GICv3CPUState;
11407e2034dSPavel Fedin
11507e2034dSPavel Fedin /* Some CPU interface registers come in three flavours:
11607e2034dSPavel Fedin * Group0, Group1 (Secure) and Group1 (NonSecure)
11707e2034dSPavel Fedin * (where the latter two are exposed as a single banked system register).
11807e2034dSPavel Fedin * In the state struct they are implemented as a 3-element array which
11907e2034dSPavel Fedin * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
12007e2034dSPavel Fedin * If the CPU doesn't support EL3 then the G1 element is unused.
12107e2034dSPavel Fedin *
12207e2034dSPavel Fedin * These constants are also used to communicate the group to use for
12307e2034dSPavel Fedin * an interrupt or SGI when it is passed between the cpu interface and
12407e2034dSPavel Fedin * the redistributor or distributor. For those purposes the receiving end
12507e2034dSPavel Fedin * must be prepared to cope with a Group 1 Secure interrupt even if it does
12607e2034dSPavel Fedin * not have security support enabled, because security can be disabled
12707e2034dSPavel Fedin * independently in the CPU and in the GIC. In that case the receiver should
12807e2034dSPavel Fedin * treat an incoming Group 1 Secure interrupt as if it were Group 0.
12907e2034dSPavel Fedin * (This architectural requirement is why the _G1 element is the unused one
13007e2034dSPavel Fedin * in a no-EL3 CPU: we would otherwise have to translate back and forth
13107e2034dSPavel Fedin * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
13207e2034dSPavel Fedin */
13307e2034dSPavel Fedin #define GICV3_G0 0
13407e2034dSPavel Fedin #define GICV3_G1 1
13507e2034dSPavel Fedin #define GICV3_G1NS 2
13607e2034dSPavel Fedin
13707e2034dSPavel Fedin /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
13807e2034dSPavel Fedin * group-related, so those indices are just 0 for S and 1 for NS.
13907e2034dSPavel Fedin * (If the CPU or the GIC, respectively, don't support the Security
14007e2034dSPavel Fedin * extensions then the S element is unused.)
14107e2034dSPavel Fedin */
14207e2034dSPavel Fedin #define GICV3_S 0
14307e2034dSPavel Fedin #define GICV3_NS 1
14407e2034dSPavel Fedin
145ce187c3cSPeter Maydell typedef struct {
146ce187c3cSPeter Maydell int irq;
147ce187c3cSPeter Maydell uint8_t prio;
148ce187c3cSPeter Maydell int grp;
1490e9f4e8eSJinjie Ruan bool nmi;
150ce187c3cSPeter Maydell } PendingIrq;
151ce187c3cSPeter Maydell
15207e2034dSPavel Fedin struct GICv3CPUState {
15307e2034dSPavel Fedin GICv3State *gic;
15407e2034dSPavel Fedin CPUState *cpu;
1553faf2b0cSPeter Maydell qemu_irq parent_irq;
1563faf2b0cSPeter Maydell qemu_irq parent_fiq;
157b53db42bSPeter Maydell qemu_irq parent_virq;
158b53db42bSPeter Maydell qemu_irq parent_vfiq;
15983f32075SJinjie Ruan qemu_irq parent_nmi;
16083f32075SJinjie Ruan qemu_irq parent_vnmi;
16107e2034dSPavel Fedin
16207e2034dSPavel Fedin /* Redistributor */
16307e2034dSPavel Fedin uint32_t level; /* Current IRQ level */
16407e2034dSPavel Fedin /* RD_base page registers */
16507e2034dSPavel Fedin uint32_t gicr_ctlr;
16607e2034dSPavel Fedin uint64_t gicr_typer;
16707e2034dSPavel Fedin uint32_t gicr_statusr[2];
16807e2034dSPavel Fedin uint32_t gicr_waker;
16907e2034dSPavel Fedin uint64_t gicr_propbaser;
17007e2034dSPavel Fedin uint64_t gicr_pendbaser;
17107e2034dSPavel Fedin /* SGI_base page registers */
17207e2034dSPavel Fedin uint32_t gicr_igroupr0;
17307e2034dSPavel Fedin uint32_t gicr_ienabler0;
17407e2034dSPavel Fedin uint32_t gicr_ipendr0;
17507e2034dSPavel Fedin uint32_t gicr_iactiver0;
1760e9f4e8eSJinjie Ruan uint32_t gicr_inmir0;
17707e2034dSPavel Fedin uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
17807e2034dSPavel Fedin uint32_t gicr_igrpmodr0;
17907e2034dSPavel Fedin uint32_t gicr_nsacr;
18007e2034dSPavel Fedin uint8_t gicr_ipriorityr[GIC_INTERNAL];
181641be697SPeter Maydell /* VLPI_base page registers */
182641be697SPeter Maydell uint64_t gicr_vpropbaser;
183641be697SPeter Maydell uint64_t gicr_vpendbaser;
18407e2034dSPavel Fedin
18507e2034dSPavel Fedin /* CPU interface */
1866692aac4SVijaya Kumar K uint64_t icc_sre_el1;
18707e2034dSPavel Fedin uint64_t icc_ctlr_el1[2];
18807e2034dSPavel Fedin uint64_t icc_pmr_el1;
18907e2034dSPavel Fedin uint64_t icc_bpr[3];
19007e2034dSPavel Fedin uint64_t icc_apr[3][4];
19107e2034dSPavel Fedin uint64_t icc_igrpen[3];
19207e2034dSPavel Fedin uint64_t icc_ctlr_el3;
193ce187c3cSPeter Maydell
1944eb833b5SPeter Maydell /* Virtualization control interface */
1954eb833b5SPeter Maydell uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */
1964eb833b5SPeter Maydell uint64_t ich_hcr_el2;
1974eb833b5SPeter Maydell uint64_t ich_lr_el2[GICV3_LR_MAX];
1984eb833b5SPeter Maydell uint64_t ich_vmcr_el2;
1994eb833b5SPeter Maydell
2004eb833b5SPeter Maydell /* Properties of the CPU interface. These are initialized from
2014eb833b5SPeter Maydell * the settings in the CPU proper.
2024eb833b5SPeter Maydell * If the number of implemented list registers is 0 then the
2034eb833b5SPeter Maydell * virtualization support is not implemented.
2044eb833b5SPeter Maydell */
2054eb833b5SPeter Maydell int num_list_regs;
2064eb833b5SPeter Maydell int vpribits; /* number of virtual priority bits */
2074eb833b5SPeter Maydell int vprebits; /* number of virtual preemption bits */
20884597ff3SPeter Maydell int pribits; /* number of physical priority bits */
20984597ff3SPeter Maydell int prebits; /* number of physical preemption bits */
2104eb833b5SPeter Maydell
211ce187c3cSPeter Maydell /* Current highest priority pending interrupt for this CPU.
212ce187c3cSPeter Maydell * This is cached information that can be recalculated from the
213ce187c3cSPeter Maydell * real state above; it doesn't need to be migrated.
214ce187c3cSPeter Maydell */
215ce187c3cSPeter Maydell PendingIrq hppi;
21617fb5e36SShashi Mallela
21717fb5e36SShashi Mallela /*
21817fb5e36SShashi Mallela * Cached information recalculated from LPI tables
21917fb5e36SShashi Mallela * in guest memory
22017fb5e36SShashi Mallela */
22117fb5e36SShashi Mallela PendingIrq hpplpi;
22217fb5e36SShashi Mallela
223c3f21b06SPeter Maydell /* Cached information recalculated from vLPI tables in guest memory */
224c3f21b06SPeter Maydell PendingIrq hppvlpi;
225c3f21b06SPeter Maydell
226ce187c3cSPeter Maydell /* This is temporary working state, to avoid a malloc in gicv3_update() */
227ce187c3cSPeter Maydell bool seenbetter;
228*28cca59cSPeter Maydell
229*28cca59cSPeter Maydell /*
230*28cca59cSPeter Maydell * Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The
231*28cca59cSPeter Maydell * CPU interface may support NMIs even when the GIC proper (what the
232*28cca59cSPeter Maydell * spec calls the IRI; the redistributors and distributor) does not.
233*28cca59cSPeter Maydell */
234*28cca59cSPeter Maydell bool nmi_support;
23507e2034dSPavel Fedin };
23607e2034dSPavel Fedin
237e5cba10eSPeter Maydell /*
238e5cba10eSPeter Maydell * The redistributor pages might be split into more than one region
239e5cba10eSPeter Maydell * on some machine types if there are many CPUs.
240e5cba10eSPeter Maydell */
241e5cba10eSPeter Maydell typedef struct GICv3RedistRegion {
242e5cba10eSPeter Maydell GICv3State *gic;
243e5cba10eSPeter Maydell MemoryRegion iomem;
244e5cba10eSPeter Maydell uint32_t cpuidx; /* index of first CPU this region covers */
245e5cba10eSPeter Maydell } GICv3RedistRegion;
246e5cba10eSPeter Maydell
24707e2034dSPavel Fedin struct GICv3State {
248ff8f06eeSShlomo Pongratz /*< private >*/
249ff8f06eeSShlomo Pongratz SysBusDevice parent_obj;
250ff8f06eeSShlomo Pongratz /*< public >*/
251ff8f06eeSShlomo Pongratz
252ff8f06eeSShlomo Pongratz MemoryRegion iomem_dist; /* Distributor */
253e5cba10eSPeter Maydell GICv3RedistRegion *redist_regions; /* Redistributor Regions */
2541e575b66SEric Auger uint32_t *redist_region_count; /* redistributor count within each region */
2551e575b66SEric Auger uint32_t nb_redist_regions; /* number of redist regions */
256ff8f06eeSShlomo Pongratz
257ff8f06eeSShlomo Pongratz uint32_t num_cpu;
258ff8f06eeSShlomo Pongratz uint32_t num_irq;
259ff8f06eeSShlomo Pongratz uint32_t revision;
260ac30dec3SShashi Mallela bool lpi_enable;
261c9e86cbdSJinjie Ruan bool nmi_support;
262ff8f06eeSShlomo Pongratz bool security_extn;
26339f29e59SPeter Maydell bool force_8bit_prio;
26407e2034dSPavel Fedin bool irq_reset_nonsecure;
265910e2048SShannon Zhao bool gicd_no_migration_shift_bug;
266ff8f06eeSShlomo Pongratz
267ff8f06eeSShlomo Pongratz int dev_fd; /* kvm device fd if backed by kvm vgic support */
26807e2034dSPavel Fedin Error *migration_blocker;
26907e2034dSPavel Fedin
2701b08e436SShashi Mallela MemoryRegion *dma;
2711b08e436SShashi Mallela AddressSpace dma_as;
2721b08e436SShashi Mallela
27307e2034dSPavel Fedin /* Distributor */
27407e2034dSPavel Fedin
27507e2034dSPavel Fedin /* for a GIC with the security extensions the NS banked version of this
27607e2034dSPavel Fedin * register is just an alias of bit 1 of the S banked version.
27707e2034dSPavel Fedin */
27807e2034dSPavel Fedin uint32_t gicd_ctlr;
27907e2034dSPavel Fedin uint32_t gicd_statusr[2];
28007e2034dSPavel Fedin GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */
28107e2034dSPavel Fedin GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */
28207e2034dSPavel Fedin GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */
28307e2034dSPavel Fedin GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */
28407e2034dSPavel Fedin GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */
28507e2034dSPavel Fedin GIC_DECLARE_BITMAP(level); /* Current level */
28607e2034dSPavel Fedin GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
2870e9f4e8eSJinjie Ruan GIC_DECLARE_BITMAP(nmi); /* GICD_INMIR */
28807e2034dSPavel Fedin uint8_t gicd_ipriority[GICV3_MAXIRQ];
28907e2034dSPavel Fedin uint64_t gicd_irouter[GICV3_MAXIRQ];
290ce187c3cSPeter Maydell /* Cached information: pointer to the cpu i/f for the CPUs specified
291ce187c3cSPeter Maydell * in the IROUTER registers
292ce187c3cSPeter Maydell */
293ce187c3cSPeter Maydell GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
29407e2034dSPavel Fedin uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
29507e2034dSPavel Fedin
29607e2034dSPavel Fedin GICv3CPUState *cpu;
2977c087bd3SPeter Maydell /* List of all ITSes connected to this GIC */
2987c087bd3SPeter Maydell GPtrArray *itslist;
29907e2034dSPavel Fedin };
30007e2034dSPavel Fedin
30107e2034dSPavel Fedin #define GICV3_BITMAP_ACCESSORS(BMP) \
30207e2034dSPavel Fedin static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \
30307e2034dSPavel Fedin { \
30407e2034dSPavel Fedin gic_bmp_set_bit(irq, s->BMP); \
30507e2034dSPavel Fedin } \
30607e2034dSPavel Fedin static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \
30707e2034dSPavel Fedin { \
30807e2034dSPavel Fedin return gic_bmp_test_bit(irq, s->BMP); \
30907e2034dSPavel Fedin } \
31007e2034dSPavel Fedin static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
31107e2034dSPavel Fedin { \
31207e2034dSPavel Fedin gic_bmp_clear_bit(irq, s->BMP); \
31307e2034dSPavel Fedin } \
31407e2034dSPavel Fedin static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \
31507e2034dSPavel Fedin int irq, int value) \
31607e2034dSPavel Fedin { \
31707e2034dSPavel Fedin gic_bmp_replace_bit(irq, s->BMP, value); \
31807e2034dSPavel Fedin }
31907e2034dSPavel Fedin
32007e2034dSPavel Fedin GICV3_BITMAP_ACCESSORS(group)
32107e2034dSPavel Fedin GICV3_BITMAP_ACCESSORS(grpmod)
32207e2034dSPavel Fedin GICV3_BITMAP_ACCESSORS(enabled)
32307e2034dSPavel Fedin GICV3_BITMAP_ACCESSORS(pending)
32407e2034dSPavel Fedin GICV3_BITMAP_ACCESSORS(active)
32507e2034dSPavel Fedin GICV3_BITMAP_ACCESSORS(level)
32607e2034dSPavel Fedin GICV3_BITMAP_ACCESSORS(edge_trigger)
3270e9f4e8eSJinjie Ruan GICV3_BITMAP_ACCESSORS(nmi)
328ff8f06eeSShlomo Pongratz
329ff8f06eeSShlomo Pongratz #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
330db1015e9SEduardo Habkost typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
3318110fa1dSEduardo Habkost DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
3328110fa1dSEduardo Habkost ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON)
333ff8f06eeSShlomo Pongratz
334db1015e9SEduardo Habkost struct ARMGICv3CommonClass {
335ff8f06eeSShlomo Pongratz /*< private >*/
336ff8f06eeSShlomo Pongratz SysBusDeviceClass parent_class;
337ff8f06eeSShlomo Pongratz /*< public >*/
338ff8f06eeSShlomo Pongratz
339ff8f06eeSShlomo Pongratz void (*pre_save)(GICv3State *s);
340ff8f06eeSShlomo Pongratz void (*post_load)(GICv3State *s);
341db1015e9SEduardo Habkost };
342ff8f06eeSShlomo Pongratz
343ff8f06eeSShlomo Pongratz void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
34401b5ab8cSPeter Maydell const MemoryRegionOps *ops);
345ff8f06eeSShlomo Pongratz
3460c40daf0SPhilippe Mathieu-Daudé /**
3470c40daf0SPhilippe Mathieu-Daudé * gicv3_class_name
3480c40daf0SPhilippe Mathieu-Daudé *
3490c40daf0SPhilippe Mathieu-Daudé * Return name of GICv3 class to use depending on whether KVM acceleration is
3500c40daf0SPhilippe Mathieu-Daudé * in use. May throw an error if the chosen implementation is not available.
3510c40daf0SPhilippe Mathieu-Daudé *
3520c40daf0SPhilippe Mathieu-Daudé * Returns: class name to use
3530c40daf0SPhilippe Mathieu-Daudé */
3540c40daf0SPhilippe Mathieu-Daudé const char *gicv3_class_name(void);
3550c40daf0SPhilippe Mathieu-Daudé
356ff8f06eeSShlomo Pongratz #endif
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