| /openbmc/linux/drivers/mtd/nand/ |
| H A D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
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| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
10 #define pr_fmt(fmt) "nand: " fmt
13 #include <linux/mtd/nand.h>
16 * nanddev_isbad() - Check if a block is bad
17 * @nand: NAND device
22 bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_isbad() argument
27 if (nanddev_bbt_is_initialized(nand)) { in nanddev_isbad()
31 entry = nanddev_bbt_pos_to_entry(nand, pos); in nanddev_isbad()
32 status = nanddev_bbt_get_block_status(nand, entry); in nanddev_isbad()
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 menu "NAND" menu
8 source "drivers/mtd/nand/onenand/Kconfig"
9 source "drivers/mtd/nand/raw/Kconfig"
10 source "drivers/mtd/nand/spi/Kconfig"
12 menu "ECC engine support"
19 bool "Software Hamming ECC engine"
26 widely used with old parts, newer NAND chips usually require
31 bool "NAND ECC Smart Media byte order"
35 Software ECC according to the Smart Media Specification.
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| H A D | ecc-mxic.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Macronix external hardware ECC engine for NAND devices, also
4 * called DPE for Data Processing Engine.
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
53 /* ECC Chunk Size */
63 /* ECC Chunk Count */
98 /* ECC machinery */
124 static struct mxic_ecc_engine *nand_to_mxic(struct nand_device *nand) in nand_to_mxic() argument
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| H A D | ecc-sw-bch.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file provides ECC correction for more than 1 bit per block of data,
14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
19 * @nand: NAND device
21 * @code: Output buffer with ECC
23 int nand_ecc_sw_bch_calculate(struct nand_device *nand, in nand_ecc_sw_bch_calculate() argument
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
29 memset(code, 0, engine_conf->code_size); in nand_ecc_sw_bch_calculate()
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
16 This file covers the generic description of a NAND chip. It implies that the
17 bus interface should not be taken into account: both raw NAND devices and
18 SPI-NAND devices are concerned by this description.
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| H A D | mxicy,nand-ecc-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Macronix NAND ECC engine
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: mxicy,nand-ecc-engine-rev3
26 - compatible
27 - reg
32 - |
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| H A D | mediatek,mtk-nfc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
15 - mediatek,mt2701-nfc
16 - mediatek,mt2712-nfc
17 - mediatek,mt7622-nfc
21 - description: Base physical address and size of NFI.
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| H A D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
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| H A D | raw-nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raw NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
19 {size} bytes for a particular raw NAND chip.
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| H A D | mediatek,nand-ecc-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
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| H A D | ingenic,nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs NAND controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
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| H A D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
17 is paired with a custom DMA engine (inventively named "Flash DMA") which
25 -- Additional SoC-specific NAND controller properties --
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| /openbmc/linux/include/linux/mtd/ |
| H A D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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| H A D | nand-ecc-sw-bch.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This file is the header for the NAND BCH ECC implementation.
11 #include <linux/mtd/nand.h>
15 * struct nand_ecc_sw_bch_conf - private software BCH ECC engine structure
17 * engine needs
19 * @calc_buf: Buffer to use when calculating ECC bytes
20 * @code_buf: Buffer to use when reading (raw) ECC bytes from the chip
23 * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
37 int nand_ecc_sw_bch_calculate(struct nand_device *nand,
39 int nand_ecc_sw_bch_correct(struct nand_device *nand, unsigned char *buf,
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| H A D | nand-ecc-sw-hamming.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com>
7 * This file is the header for the NAND Hamming ECC implementation.
13 #include <linux/mtd/nand.h>
16 * struct nand_ecc_sw_hamming_conf - private software Hamming ECC engine structure
18 * engine needs
20 * @calc_buf: Buffer to use when calculating ECC bytes
21 * @code_buf: Buffer to use when reading (raw) ECC bytes from the chip
34 int nand_ecc_sw_hamming_init_ctx(struct nand_device *nand);
35 void nand_ecc_sw_hamming_cleanup_ctx(struct nand_device *nand);
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| /openbmc/u-boot/doc/ |
| H A D | README.nand | 1 # SPDX-License-Identifier: GPL-2.0+
2 NAND FLASH commands and notes
12 nand bad
15 nand device
16 Print information about the current NAND device.
18 nand device num
21 nand erase off|partition size
22 nand erase clean [off|partition size]
32 If `clean' is specified, a JFFS2-style clean marker is written to
40 nand info
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | mediatek,spi-mtk-snfi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
14 the Mediatek NAND flash controller. It can perform standard SPI
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
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| H A D | mxicy,mx25f0a-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mxicy,mx25f0a-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: spi-controller.yaml#
17 const: mxicy,mx25f0a-spi
23 reg-names:
25 - const: regs
26 - const: dirmap
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 2 menuconfig NAND config
3 bool "Raw NAND Device Support"
4 if NAND
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
19 bool "Support Atmel NAND controller"
22 Enable this driver for NAND flash platforms using an Atmel NAND
28 bool "Atmel Hardware ECC"
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| H A D | omap_gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
15 #include <nand.h>
54 * omap_nand_hwcontrol - Set the address pointers corretly for the
62 int cs = info->cs; in omap_nand_hwcontrol()
70 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; in omap_nand_hwcontrol()
73 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; in omap_nand_hwcontrol()
76 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; in omap_nand_hwcontrol()
81 writeb(cmd, this->IO_ADDR_W); in omap_nand_hwcontrol()
89 return gpmc_cfg->status & (1 << (8 + info->ws)); in omap_dev_ready()
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| H A D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 #include <nand.h>
15 #include <asm/arch-tegra/clk_rst.h>
29 /* ECC bytes to be generated for tag data */
34 .compatible = "nvidia,tegra20-nand",
41 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
43 * Main area Ecc(36)
45 * Tag data Ecc(4)
87 /* Information about an attached NAND chip */
91 struct gpio_desc wp_gpio; /* write-protect GPIO */
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | omap2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
21 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
145 struct nand_chip nand; member
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Raw/Parallel NAND Device Support"
8 NAND flash devices. For further information see
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
13 comment "Raw/parallel NAND flash controllers"
19 tristate "Denali NAND controller on Intel Moorestown"
23 Enable the driver for NAND flash on Intel Moorestown, using the
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
31 Enable the driver for NAND flash on platforms using a Denali NAND
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| /openbmc/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
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