13af7ade2SXiangsheng Hou# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 23af7ade2SXiangsheng Hou%YAML 1.2 33af7ade2SXiangsheng Hou--- 43af7ade2SXiangsheng Hou$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml# 53af7ade2SXiangsheng Hou$schema: http://devicetree.org/meta-schemas/core.yaml# 63af7ade2SXiangsheng Hou 73af7ade2SXiangsheng Houtitle: MediaTek(MTK) SoCs NAND ECC engine 83af7ade2SXiangsheng Hou 93af7ade2SXiangsheng Houmaintainers: 103af7ade2SXiangsheng Hou - Xiangsheng Hou <xiangsheng.hou@mediatek.com> 113af7ade2SXiangsheng Hou 123af7ade2SXiangsheng Houdescription: | 133af7ade2SXiangsheng Hou MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. 143af7ade2SXiangsheng Hou 153af7ade2SXiangsheng Houproperties: 163af7ade2SXiangsheng Hou compatible: 173af7ade2SXiangsheng Hou enum: 183af7ade2SXiangsheng Hou - mediatek,mt2701-ecc 193af7ade2SXiangsheng Hou - mediatek,mt2712-ecc 203af7ade2SXiangsheng Hou - mediatek,mt7622-ecc 21*70d3cf76SXiangsheng Hou - mediatek,mt7986-ecc 223af7ade2SXiangsheng Hou 233af7ade2SXiangsheng Hou reg: 243af7ade2SXiangsheng Hou items: 253af7ade2SXiangsheng Hou - description: Base physical address and size of ECC. 263af7ade2SXiangsheng Hou 273af7ade2SXiangsheng Hou interrupts: 283af7ade2SXiangsheng Hou items: 293af7ade2SXiangsheng Hou - description: ECC interrupt 303af7ade2SXiangsheng Hou 313af7ade2SXiangsheng Hou clocks: 323af7ade2SXiangsheng Hou maxItems: 1 333af7ade2SXiangsheng Hou 343af7ade2SXiangsheng Hou clock-names: 353af7ade2SXiangsheng Hou const: nfiecc_clk 363af7ade2SXiangsheng Hou 373af7ade2SXiangsheng Hourequired: 383af7ade2SXiangsheng Hou - compatible 393af7ade2SXiangsheng Hou - reg 403af7ade2SXiangsheng Hou - interrupts 413af7ade2SXiangsheng Hou - clocks 423af7ade2SXiangsheng Hou - clock-names 433af7ade2SXiangsheng Hou 443af7ade2SXiangsheng HouadditionalProperties: false 453af7ade2SXiangsheng Hou 463af7ade2SXiangsheng Houexamples: 473af7ade2SXiangsheng Hou - | 483af7ade2SXiangsheng Hou #include <dt-bindings/clock/mt2701-clk.h> 493af7ade2SXiangsheng Hou #include <dt-bindings/interrupt-controller/arm-gic.h> 503af7ade2SXiangsheng Hou #include <dt-bindings/interrupt-controller/irq.h> 513af7ade2SXiangsheng Hou 523af7ade2SXiangsheng Hou soc { 533af7ade2SXiangsheng Hou #address-cells = <2>; 543af7ade2SXiangsheng Hou #size-cells = <2>; 553af7ade2SXiangsheng Hou 563af7ade2SXiangsheng Hou bch: ecc@1100e000 { 573af7ade2SXiangsheng Hou compatible = "mediatek,mt2701-ecc"; 583af7ade2SXiangsheng Hou reg = <0 0x1100e000 0 0x1000>; 593af7ade2SXiangsheng Hou interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; 603af7ade2SXiangsheng Hou clocks = <&pericfg CLK_PERI_NFI_ECC>; 613af7ade2SXiangsheng Hou clock-names = "nfiecc_clk"; 623af7ade2SXiangsheng Hou }; 633af7ade2SXiangsheng Hou }; 64