/openbmc/linux/Documentation/i2c/ |
H A D | i2c-topology.rst | 6 than a straight-forward I2C bus with one adapter and one or more devices. 10 1. A mux may be needed on the bus to prevent address collisions. 25 I2C transfers, and all adapters with a parent are part of an "i2c-mux" 28 Depending of the particular mux driver, something happens when there is 29 an I2C transfer on one of its child adapters. The mux driver can 30 obviously operate a mux, but it can also do arbitration with an external 31 bus master or open a gate. The mux driver has two operations for this, 40 mux-locked or parent-locked muxes. 43 Mux-locked muxes 44 ---------------- [all …]
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/openbmc/linux/Documentation/devicetree/bindings/i2c/ |
H A D | i2c-mux-gpmux.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: General Purpose I2C Bus Mux 10 - Peter Rosin <peda@axentia.se> 13 This binding describes an I2C bus multiplexer that uses a mux controller 14 from the mux subsystem to route the I2C signals. 16 .-----. .-----. 18 .------------. '-----' '-----' [all …]
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/openbmc/linux/drivers/i2c/ |
H A D | i2c-mux.c | 4 * Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it> 5 * Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it> 6 * Copyright (c) 2009-2010 NSN GmbH & Co KG <michael.lawnick.ext@nsn.com> 10 * Supports multi-level mux'ing (mux behind a mux). 13 * i2c-virt.c from Kumar Gala <galak@kernel.crashing.org> 14 * i2c-virtual.c from Ken Harrenstien, Copyright (c) 2004 Google, Inc. 15 * i2c-virtual.c from Brian Kuschak <bkuschak@yahoo.com> 24 #include <linux/i2c-mux.h> 42 struct i2c_mux_priv *priv = adap->algo_data; in __i2c_mux_master_xfer() 43 struct i2c_mux_core *muxc = priv->muxc; in __i2c_mux_master_xfer() [all …]
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/openbmc/linux/drivers/mux/ |
H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0 10 #define pr_fmt(fmt) "mux-core: " fmt 19 #include <linux/mux/consumer.h> 20 #include <linux/mux/driver.h> 25 * The idle-as-is "state" is not an actual state that may be selected, it 32 * struct mux_state - Represents a mux controller state specific to a given 34 * @mux: Pointer to a mux controller. 35 * @state: State of the mux to be selected. 41 struct mux_control *mux; member 46 .name = "mux", [all …]
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/openbmc/linux/drivers/i2c/muxes/ |
H A D | i2c-mux-gpmux.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/i2c-mux.h> 13 #include <linux/mux/consumer.h> 17 struct mux { struct 25 struct mux *mux = i2c_mux_priv(muxc); in i2c_mux_select() argument 28 ret = mux_control_select(mux->control, chan); in i2c_mux_select() 29 mux->do_not_deselect = ret < 0; in i2c_mux_select() 36 struct mux *mux = i2c_mux_priv(muxc); in i2c_mux_deselect() local 38 if (mux->do_not_deselect) in i2c_mux_deselect() 41 return mux_control_deselect(mux->control); in i2c_mux_deselect() [all …]
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H A D | i2c-mux-pinctrl.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <linux/i2c-mux.h> 24 struct i2c_mux_pinctrl *mux = i2c_mux_priv(muxc); in i2c_mux_pinctrl_select() local 26 return pinctrl_select_state(mux->pinctrl, mux->states[chan]); in i2c_mux_pinctrl_select() 31 return i2c_mux_pinctrl_select(muxc, muxc->num_adapters); in i2c_mux_pinctrl_deselect() 41 list_for_each_entry(setting, &state->settings, node) { in i2c_mux_pinctrl_root_adapter() 42 pin_root = i2c_root_adapter(setting->pctldev->dev); in i2c_mux_pinctrl_root_adapter() 56 struct device_node *np = dev->of_node; in i2c_mux_pinctrl_parent_adapter() 60 parent_np = of_parse_phandle(np, "i2c-parent", 0); in i2c_mux_pinctrl_parent_adapter() 62 dev_err(dev, "Cannot parse i2c-parent\n"); in i2c_mux_pinctrl_parent_adapter() [all …]
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H A D | i2c-mux-gpio.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <linux/i2c-mux.h> 11 #include <linux/platform_data/i2c-mux-gpio.h> 26 static void i2c_mux_gpio_set(const struct gpiomux *mux, unsigned val) in i2c_mux_gpio_set() argument 32 gpiod_set_array_value_cansleep(mux->ngpios, mux->gpios, NULL, values); in i2c_mux_gpio_set() 37 struct gpiomux *mux = i2c_mux_priv(muxc); in i2c_mux_gpio_select() local 39 i2c_mux_gpio_set(mux, chan); in i2c_mux_gpio_select() 46 struct gpiomux *mux = i2c_mux_priv(muxc); in i2c_mux_gpio_deselect() local 48 i2c_mux_gpio_set(mux, mux->data.idle); in i2c_mux_gpio_deselect() 53 static int i2c_mux_gpio_probe_fw(struct gpiomux *mux, in i2c_mux_gpio_probe_fw() argument [all …]
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/openbmc/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_pbs.c | 1 // SPDX-License-Identifier: GPL-2.0 44 /* PBS locked dq (per pup) */ 92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx() 102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx() 104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx() 105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx() 110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx() 111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx() 113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx() 116 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx() [all …]
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H A D | ddr3_read_leveling.c | 1 // SPDX-License-Identifier: GPL-2.0 56 * Args: dram_info - main struct 57 * freq - current sequence frequency 65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw() 66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw() 74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw() 76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw() 93 dram_info->rl_max_phase = 0; in ddr3_read_leveling_hw() 94 dram_info->rl_min_phase = 10; in ddr3_read_leveling_hw() 98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw() [all …]
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H A D | ddr3_dqs.c | 1 // SPDX-License-Identifier: GPL-2.0 55 /* State machine for centralization - find low & high limit */ 97 switch (dram_info->ddr_width) { in ddr3_dqs_choose_pattern() 135 DEBUG_DQS_S("DDR3 - DQS Centralization RX - Starting procedure\n"); in ddr3_dqs_centralization_rx() 141 /* [0] = 1 - Enable SW override */ in ddr3_dqs_centralization_rx() 142 /* 0x15B8 - Training SW 2 Register */ in ddr3_dqs_centralization_rx() 144 DEBUG_DQS_S("DDR3 - DQS Centralization RX - SW Override Enabled\n"); in ddr3_dqs_centralization_rx() 147 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_rx() 151 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx() 152 DEBUG_DQS_FULL_C("DDR3 - DQS Centralization RX - CS - ", in ddr3_dqs_centralization_rx() [all …]
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/openbmc/linux/arch/arm/boot/dts/microchip/ |
H A D | at91-natte.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * at91-natte.dts - Device Tree include file for the Natte board 11 mux: mux-controller { label 12 compatible = "gpio-mux"; 13 #mux-control-cells = <0>; 15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>, 20 batntc-mux { 21 compatible = "io-channel-mux"; 22 io-channels = <&adc 5>; 23 io-channel-names = "parent"; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | qoriq-clock.txt | 5 multiple phase locked loops (PLL) to create a variety of frequencies 14 --------------- ------------- 21 - compatible: Should contain a chip-specific clock block compatible 22 string and (if applicable) may contain a chassis-version clock 25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as: 26 * "fsl,p2041-clockgen" 27 * "fsl,p3041-clockgen" 28 * "fsl,p4080-clockgen" 29 * "fsl,p5020-clockgen" 30 * "fsl,p5040-clockgen" [all …]
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/openbmc/linux/drivers/spi/ |
H A D | spi-dw-bt1.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 // Baikal-T1 DW APB SPI and System Boot SPI driver 17 #include <linux/mux/consumer.h> 24 #include <linux/spi/spi-mem.h> 27 #include "spi-dw.h" 35 struct mux_control *mux; member 52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create() 54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create() 55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create() 56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create() [all …]
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/openbmc/linux/drivers/mtd/nand/onenand/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 48 a One-Time Programmable Block memory area. 51 The OTP block can be read, programmed and locked using the same 55 OTP block is fully-guaranteed to be a valid block. 61 Since the device is equipped with two DataRAMs, and two-plane NAND 69 Mux: KFM2G16Q2M, KFN4G16Q2M,
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/openbmc/u-boot/board/samsung/odroid/ |
H A D | odroid.c | 1 // SPDX-License-Identifier: GPL-2.0+ 37 /* Set GPA1 pin 1 to HI - enable XCL205 output */ in set_board_type() 43 /* Set GPC1 pin 2 to IN - check XCL205 output state */ in set_board_type() 47 /* XCL205 - needs some latch time */ in set_board_type() 50 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */ in set_board_type() 52 gd->board_type = ODROID_TYPE_X2; in set_board_type() 54 gd->board_type = ODROID_TYPE_U3; in set_board_type() 69 return board_type[gd->board_type]; in get_board_type() 120 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); in board_clock_init() 122 /* Wait for mux change */ in board_clock_init() [all …]
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/openbmc/linux/drivers/media/i2c/ |
H A D | max9286.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2017-2019 Jacopo Mondi 6 * Copyright (C) 2017-2019 Kieran Bingham 7 * Copyright (C) 2017-2019 Laurent Pinchart 8 * Copyright (C) 2017-2019 Niklas Söderlund 20 #include <linux/i2c-mux.h> 27 #include <media/v4l2-async.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-fwnode.h> [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
H A D | clock.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 26 * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in 27 * those cases, nothing is stored in the bits about the mux field, so it's 28 * safe to pretend that the mux field extends all the way to the end of the 29 * register. As such, the U-Boot clock driver is currently a bit lazy, and 39 #include <asm/arch/clock-tables.h> 71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) 77 * Read low-level parameters of a PLL. 86 * @returns 0 if ok, -1 on error (invalid clock id) 143 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) [all …]
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/openbmc/linux/net/kcm/ |
H A D | kcmsock.c | 1 // SPDX-License-Identifier: GPL-2.0-only 46 return (struct kcm_tx_msg *)skb->cb; in kcm_tx_msg() 51 csk->sk_err = EPIPE; in report_csk_error() 58 struct sock *csk = psock->sk; in kcm_abort_tx_psock() 59 struct kcm_mux *mux = psock->mux; in kcm_abort_tx_psock() local 63 spin_lock_bh(&mux->lock); in kcm_abort_tx_psock() 65 if (psock->tx_stopped) { in kcm_abort_tx_psock() 66 spin_unlock_bh(&mux->lock); in kcm_abort_tx_psock() 70 psock->tx_stopped = 1; in kcm_abort_tx_psock() 71 KCM_STATS_INCR(psock->stats.tx_aborts); in kcm_abort_tx_psock() [all …]
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/openbmc/linux/drivers/clk/davinci/ |
H A D | da8xx-cfgchip.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP 8 #include <linux/clk-provider.h> 12 #include <linux/mfd/da8xx-cfgchip.h> 16 #include <linux/platform_data/clk-da8xx-cfgchip.h> 21 /* --- Gate clocks --- */ 46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); in da8xx_cfgchip_gate_clk_enable() 53 regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); in da8xx_cfgchip_gate_clk_disable() 61 regmap_read(clk->regmap, clk->reg, &val); in da8xx_cfgchip_gate_clk_is_enabled() 63 return !!(val & clk->mask); in da8xx_cfgchip_gate_clk_is_enabled() [all …]
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/openbmc/u-boot/board/compulab/cm_t43/ |
H A D | cm_t43.c | 1 // SPDX-License-Identifier: GPL-2.0+ 33 /* We don't care if fseal is locked, but we do need it set */ in power_init_board() 45 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init() 120 if (phydev->drv->config) in board_phy_config() 121 return phydev->drv->config(phydev); in board_phy_config() 129 writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ in board_phy_init() 155 writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); in board_eth_init()
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/openbmc/linux/include/linux/mfd/ |
H A D | intel-m10-bmc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 5 * Copyright (C) 2018-2020 Intel Corporation, Inc. 164 #define get_flash_mux(mux) FIELD_GET(M10BMC_N6000_FLASH_MUX_SELECTION, mux) argument 188 * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map 211 * struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information 229 * struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W 236 * is locked, @read returns -EBUSY. 253 * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure 274 * m10bmc_raw_read - read m10bmc register per addr 275 * m10bmc_sys_read - read m10bmc system register per offset [all …]
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/openbmc/linux/drivers/tty/serial/ |
H A D | dz.c | 1 // SPDX-License-Identifier: GPL-2.0 12 * [31-AUG-98] triemer 14 * removed base_addr code - moving address assignment to setup.c 16 * [13-NOV-98] triemer fixed code to receive characters 18 * [09-JAN-99] triemer minor fix for schedule - due to removal of timeout 19 * field from "current" - somewhere between 2.1.121 and 2.1.131 21 * [27-JUN-2001] Arnaldo Carvalho de Melo <acme@conectiva.com.br> - cleanups 24 * [07-SEP-99] Bugfixes 26 * [06-Jan-2002] Russell King <rmk@arm.linux.org.uk> 71 struct dz_mux *mux; member [all …]
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/openbmc/u-boot/board/logicpd/omap3som/ |
H A D | omap3logic.c | 1 // SPDX-License-Identifier: GPL-2.0+ 10 * Richard Woodruff <r-woodruff2@ti.com> 23 #include <asm/arch/mux.h> 28 #include <asm/mach-types.h> 38 #include <asm/ehci-omap.h> 62 /* break into full u-boot on 'c' */ in spl_start_uboot() 70 * Description: If we use SPL then there is no x-loader nor config header 77 timings->mr = MICRON_V_MR_165; in get_board_mem_timings() 82 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings() 83 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings() [all …]
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/openbmc/linux/drivers/clk/xilinx/ |
H A D | xlnx_vcu.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016 - 2017 Xilinx, Inc. 11 #include <linux/clk-provider.h> 16 #include <linux/mfd/syscon/xlnx-vcu.h> 22 #include <dt-bindings/clock/xlnx-vcu.h> 50 * struct xvcu_device - Xilinx VCU init device structure 81 * struct xvcu_pll_cfg - Helper data 203 * xvcu_read - Read from the VCU register space 216 * xvcu_write - Write to the VCU register space 237 void __iomem *base = pll->reg_base; in xvcu_pll_wait_for_lock() [all …]
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/openbmc/linux/drivers/media/dvb-frontends/ |
H A D | mxl692_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 23 #define MXL_EAGLE_VERSION_SIZE 5 /* A.B.C.D-RCx */ 226 /* Enum of I/O Mux function, used in device I/O mux configuration API */ 271 MXL_EAGLE_QAM_DEMOD_ANNEX_A, /* DVB-C */ 295 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_0_772MHZ, /* ANSI/SCTE 55-2 0.772 MHz */ 296 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_024MHZ, /* ANSI/SCTE 55-1 1.024 MHz */ 297 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_544MHZ, /* ANSI/SCTE 55-2 1.544 MHz */ 509 u8 locked; member
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