| /openbmc/u-boot/drivers/gpio/ |
| H A D | mvmfp.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
16 * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
17 * configuration registers to configure each GPIO/Function pin on the
20 * This function reads the array of values for
22 * Multi-Function Pin registers.
23 * It supports - Alternate Function Selection programming.
51 * perform a read-back of any MFPR register to make sure the in mfp_config()
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| /openbmc/phosphor-power/phosphor-power-supply/docs/ |
| H A D | MultiChassis.md | 1 # Multi-Chassis Support for phosphor-psu-monitor
5 Currently, **phosphor-psu-monitor** operates on a **single chassis**.
7 - It gets the PSUs device access information (such as PSU I2CBus and I2CAddress)
9 - The phosphor-psu-monitor uses a **fixed object path**, appended with the PSU
11 - Example of current PSU path:
18 ## Goal: Support Multi-Chassis PSUs
20 To support **multi-chassis**, the **phosphor-psu-monitor** requires the
23 - Define Chassis class
24 - Modify the **PSUManager** class to instantiate one **Chassis class** per
26 - Find all PSUs associated with each chassis.
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| /openbmc/u-boot/doc/driver-model/ |
| H A D | pmic-framework.txt | 2 # (C) Copyright 2014-2015 Samsung Electronics
5 # SPDX-License-Identifier: GPL-2.0+
18 This is an introduction to driver-model multi uclass PMIC IC's support.
20 - UCLASS_PMIC - basic uclass type for PMIC I/O, which provides common
22 - UCLASS_REGULATOR - additional uclass type for specific PMIC features,
27 - drivers/power/pmic/pmic-uclass.c
28 - include/power/pmic.h
30 - drivers/power/regulator/regulator-uclass.c
31 - include/power/regulator.h
34 - common/cmd_pmic.c
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| /openbmc/u-boot/doc/device-tree-bindings/timer/ |
| H A D | atcpit100_timer.txt | 2 ------------------------------------------------------------------
6 This timer is a set of compact multi-function timers, which can be
10 multi-function timer and provide the following usage scenarios:
11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
16 Two 8-bit timer and one 8-bit PWM
19 - compatible : Should be "andestech,atcpit100"
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| /openbmc/u-boot/include/ |
| H A D | adc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
10 /* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */
13 /* The last possible selected channel with 32-bit mask */
19 * - ADC_DATA_FORMAT_BIN - binary offset
20 * - ADC_DATA_FORMAT_2S - two's complement
31 * struct adc_channel - structure to hold channel conversion data.
32 * Useful to keep the result of a multi-channel conversion output.
34 * @id - channel id
35 * @data - channel conversion data
43 * struct adc_uclass_platdata - basic ADC info
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| H A D | bootm.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2000-2009
13 #define BOOTM_ERR_RESET (-1)
14 #define BOOTM_ERR_OVERLAP (-2)
15 #define BOOTM_ERR_UNIMPLEMENTED (-3)
19 * - copied image header to global variable `header'
20 * - checked header magic number, checksums (both header & image),
21 * - verified image architecture (PPC) and type (KERNEL or MULTI),
22 * - loaded (first part of) image to header load address,
23 * - disabled interrupts.
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| /openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/images/ |
| H A D | fb-yosemite4-phosphor-image.inc | 2 # causing that multi-user.target never complete.
3 # If multi-user.target doesn't complete,
4 # the obmc-host-startmin@.target couldn't start.
7 # Temporarily add libusb1 to allow side-loading of a BIOS/BIC update
13 # Temporarily add plat-svc for gpio initialization
15 plat-svc \
17 # Enable obmc-phosphor-buttons which needed by debug card function.
19 phosphor-gpio-monitor \
20 obmc-phosphor-buttons-signals \
21 obmc-phosphor-buttons-handler \
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| /openbmc/u-boot/doc/device-tree-bindings/pinctrl/ |
| H A D | marvell,mvebu-pinctrl.txt | 1 The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
2 pins (mpp) to a specific function.
4 be used for a specific device or function. Each node requires one or more
5 mpp pins or group of pins and a mpp function common to all pins.
8 - compatible: "marvell,mvebu-pinctrl",
9 "marvell,ap806-pinctrl",
10 "marvell,armada-7k-pinctrl",
11 "marvell,armada-8k-cpm-pinctrl",
12 "marvell,armada-8k-cps-pinctrl"
13 - bank-name: A string defining the pinc controller bank name
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| /openbmc/u-boot/doc/ |
| H A D | README.bitbangMII | 1 This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
4 buses are implemented via bit-banging mode.
9 CONFIG_BITBANGMII - Enable the miiphybb driver
10 CONFIG_BITBANGMII_MULTI - Enable the multi bus support
15 MII_INIT - Generic code to enable the MII bus (optional)
16 MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
17 MDIO_ACTIVE - Activate the MDIO pin as out pin
18 MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
19 MDIO_READ - Read the MDIO pin
20 MDIO(v) - Write v on the MDIO pin
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| H A D | README.power-framework | 5 # SPDX-License-Identifier: GPL-2.0+
9 ------------
11 This document describes the second version of the u-boot's PMIC (Power
16 ----------
18 Boards supported by u-boot are getting increasingly complex. Developers and
20 devices are now available on the board - namely power managers (PMIC), fuel
21 gauges (FG), micro USB interface controllers (MUIC), batteries, multi-function
25 -----------------------------------
28 The same device - e.g. MAX8997 uses two different I2C busses and addresses.
33 pmic_req_write() function.
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| H A D | README.sched | 4 'sched.c' provides an very simplistic multi-threading scheduler.
5 See the example, function 'sched(...)', in the same file for its
16 - There are NO primitives for thread synchronization (locking,
19 - Only the GPRs and FPRs context is saved during a thread context
23 - The scheduler is NOT transparent to the user. The user
27 - There are NO priorities, and the scheduling policy is round-robin
30 - There are NO capabilities to collect thread CPU usage, scheduler
33 - The semantics are somewhat based on those of pthreads, but NOT
36 - Only seven threads are allowed. These can be easily increased by
39 - The stack size of each thread is 8KBytes. This can be easily
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/State/ |
| H A D | README.md | 5 The goal of the phosphor-state-manager repository is to control and track the
32 power to the chassis. The Chassis being on is a pre-req to the Host being
66 In multi-host or multi-chassis system, instance number can be used from 1-N, as
67 0 is reserved for complete system. In multi chassis system this can be named as
88 multi-chassis system, starting counting from 1 rather than 0 would avoid this
91 to function on this multi-chassis system.
99 that code will continue to function, or error out rather than doing something
120 spec (DSP0249, Section 6.3, State Sets Tables, Table 7 – Boot-Related State
121 Sets, Set ID - 196 Boot Progress).
124 …https://github.com/openbmc/docs/blob/master/architecture/openbmc-systemd.md#error-handling-of-syst…
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/ |
| H A D | Chassis.interface.yaml | 5 - name: Type
12 - name: ChassisType
16 - name: Blade
18 An enclosed or semi-enclosed, typically vertically-oriented,
19 system chassis that must be plugged into a multi-system chassis
20 to function normally.
21 - name: Component
24 particular subsystem or function.
25 - name: Enclosure
29 - name: Module
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| /openbmc/openbmc-test-automation/lib/ |
| H A D | bmc_network_utils.py | 32 stdout = subprocess.check_output(["hostname", "--all-fqdns"], shell=True)
33 host_fqdns = stdout.decode("utf-8").strip()
71 Starting Nping 0.6.47 ( http://nmap.org/nping ) at 2019-08-07 22:05 IST
83 Example of data returned by this function:
119 nping_result["lost"].split(" ")[-1].strip("()%")
123 nping_result["failed"].split(" ")[-1].strip("()%")
137 Note that any valid nping argument may be specified as a function argument.
141 ${nping_result}= Nping delay=${delay} count=${count} icmp=${None} icmp-type=echo
158 parse_results 1 or True indicates that this function
162 function for details on the dictionary
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| /openbmc/docs/designs/ |
| H A D | bmc-boot-ready.md | 33 `multi-user.target` has successfully started all if its services.
37 1. D-Bus objects don't exist until the backend is prepared to handle them.
43 Option 1 is challenging because D-Bus interfaces provided by OpenBMC state
44 applications have a mix of read-only properties (like current state) and
51 the op-panel code now need to properly handle error codes like this. You can
60 [1]: https://lists.ozlabs.org/pipermail/openbmc/2022-April/030175.html
62 https://github.com/openbmc/phosphor-dbus-interfaces/tree/master/yaml/xyz/openbmc_project/State
64 …https://github.com/openbmc/phosphor-dbus-interfaces/blob/master/yaml/xyz/openbmc_project/State/BMC…
68 - Queue up chassis and host requested state changes until the BMC is in the
70 - What the "proper state" is will be implementation specific but by default
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| /openbmc/docs/architecture/ |
| H A D | ipmi-architecture.md | 8 ## High-Level Overview
18 /------------------\
19 /----------------------------\ | |
20 | KCS/BT - Host | <-All IPMI cmds-> | |
22 \----------------------------/ | IPMI Daemon |
25 /-----------------------------\ | |
26 | LAN - RMCP+ | | |
27 | /--------------------------\| | |
28 | |*Process the Session and || <-All IPMI cmds-> | |
31 | \--------------------------/| | |
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| /openbmc/phosphor-webui/app/common/directives/ |
| H A D | dirPagination.js | 2 * dirPagination - AngularJS module for paginating (almost) anything.
10 * https://groups.google.com/d/msg/angular/an9QpzqIYiM/r8v-3W1X5vcJ for the idea
11 * on how to dynamically invoke the ng-repeat directive.
15 * https://github.com/angular-ui/bootstrap/blob/master/src/pagination/pagination.js
20 (function() {
47 function dirPaginateDirective($compile, $parse, paginationService) {
55 function dirPaginationCompileFn(tElement, tAttrs) {
72 // If any value is specified for paginationId, we register the un-evaluated
73 // expression at this stage for the benefit of any dir-pagination-controls
78 return function dirPaginationLinkFn(scope, element, attrs) {
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| /openbmc/sdbusplus/include/sdbusplus/sdbuspp_support/ |
| H A D | server.hpp | 7 /** This file contains support functions for sdbus++-generated server
21 * @param[in] f The interface function for the get/set.
23 * This function will unpack a message's contents, redirect them to the
24 * function 'f', and then pack them into the response message.
28 sd_bus_error* error, std::function<Return(Args&&...)> f) in property_callback()
42 // Call the function with the arguments. in property_callback()
66 * @tparam multi_return Set to true if the function returns multiple results.
67 * Otherwise, this function is unable to differentiate
75 * @param[in] f The interface function for the get/set.
77 * @return a negative return-code on error.
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| /openbmc/qemu/tests/unit/ |
| H A D | test-aio-multithread.c | 10 * See the COPYING.LIB file in the top-level directory.
17 #include "qemu/error-report.h"
26 static __thread int id = -1;
30 /* Run a function synchronously on a remote iothread. */
41 data->cb(data->arg); in ctx_run_bh_cb()
201 /* CoMutex thread-safety. */
297 static int mutex_head = -1;
303 nodes[id].next = -1; in mcs_mutex_lock()
306 if (prev != -1) { in mcs_mutex_lock()
317 if (qatomic_read(&nodes[id].next) == -1) { in mcs_mutex_unlock()
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| /openbmc/u-boot/drivers/power/pmic/ |
| H A D | pmic_tps65217.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011-2013
14 * tps65217_reg_read() - Generic function that can read a TPS65217 register
29 * tps65217_reg_write() - Generic function that can write a TPS65217 PMIC
38 * @mask: Bit mask (8 bits) to be applied. Function will only
112 * tps65217_voltage_update() - Function to change a voltage level, as this
113 * is a multi-step process.
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| H A D | pmic_tps62362.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
18 * tps62362_voltage_update() - Function to change a voltage level, as this
19 * is a multi-step process.
33 return -ENODEV; in tps62362_voltage_update()
46 return -ENOMEM; in power_tps62362_init()
49 p->name = name; in power_tps62362_init()
50 p->interface = PMIC_I2C; in power_tps62362_init()
51 p->number_of_regs = TPS62362_NUM_REGS; in power_tps62362_init()
52 p->hw.i2c.addr = TPS62362_I2C_ADDR; in power_tps62362_init()
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| /openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/templates/ |
| H A D | basetable_bottom.html | 4 <!-- Show pagination controls -->
5 <div id="pagination-basetable_bottom">
6 …<!--span class="help-inline">Showing {{objects.start_index}} to {{objects.end_index}} out of {{obj…
23 <form class="navbar-form navbar-right">
24 <div class="form-group">
26 <select class="form-control pagesize">
37 <!-- Update page display settings -->
40 $(document).ready(function() {
69 $('.chbxtoggle').each(function () {
73 //turn edit columns dropdown into a multi-select menu
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| /openbmc/u-boot/drivers/pinctrl/ |
| H A D | Kconfig | 19 This provides Linux-compatible device tree interface for the pinctrl
24 If this option is disabled (it is the only possible choice for non-DT
27 It is totally up to the implementation of each low-level driver.
40 If you need to handle vendor-specific DT properties, you can disable
52 allows the required function to be selected for each pin.
66 This option is an SPL-variant of the PINCTRL option.
75 This option is an SPL-variant of the PINCTRL_FULL option.
83 This option is an SPL-variant of the PINCTRL_GENERIC option.
91 This option is an SPL-variant of the PINMUX option.
96 to adjust pin multiplexing in SPL in order to boot into U-Boot,
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| /openbmc/qemu/docs/devel/ |
| H A D | reset.rst | 18 ----------------
43 have some non-deterministic state they want to reinitialize to a different
45 must not reinitialize on a snapshot-load reset.
49 its devices during wake-up (from the ``MachineClass::wakeup()`` method), this
51 type to differentiate the reset requested during machine wake-up from other
52 reset requests. For example, RAM content must not be lost during wake-up, and
53 memory devices like virtio-mem that provide additional RAM must not reset
54 such state during wake-ups, but might do so during cold resets. However, this
55 reset type should not be used for wake-up detection, as not every machine
56 type issues a device reset request during wake-up.
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| /openbmc/u-boot/include/power/ |
| H A D | pmic.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014-2015 Samsung Electronics
6 * Copyright (C) 2011-2012 Samsung Electronics
89 * U-Boot PMIC Framework
92 * UCLASS_PMIC - This is designed to provide an I/O interface for PMIC devices.
94 * For the multi-function PMIC devices, this can be used as parent I/O device
100 * |_ BUS 0 device (e.g. I2C0) - UCLASS_I2C/SPI/...
101 * | |_ PMIC device (READ/WRITE ops) - UCLASS_PMIC
102 * | |_ REGULATOR device (ldo/buck/... ops) - UCLASS_REGULATOR
103 * | |_ CHARGER device (charger ops) - UCLASS_CHARGER (in the future)
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